Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-06-22
2001-03-27
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S753000, C257S763000, C257S759000
Reexamination Certificate
active
06208032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, in particular, to a compound semiconductor device using gold plating and a fabrication method thereof.
2. Description of the Related Art
As the density and integration of semiconductor devices have become high, a multi-layer wiring structure has been widely used. With such a structure, in addition to the accomplishment of high integration, a wiring pattern can be easily designed. However, as drawbacks of the multi-layer wiring structure, the number of fabrication steps increases. In addition, the front surface of a multi-layer wiring structure unsmooths. When the surface of the multi-layer wiring structure unsmooths, a wire breakage and a migration will take place. Thus, the smoothness of the front surface of the multi-layer wiring structure is very important.
The multi-layer wiring structure is obtained as follows: contact holes are formed in a substrate. Metal is clad and patterned. An insulation layer is disposed on the patterned metal. After a predetermined number of layers are formed, bonding pads are formed.
Film materials used for the multi-layer wiring structure are metal films and insulation films. Preferred characteristics of the metal films include a good step coverage, a low resistance, a high ohmic contact to the substrate, a good adhesion to the base material of the insulation film, an easy patterning characteristic, uniform and homogeneous, a high migration resistance, and chemical and thermal stabilities. Preferred characteristics of the insulation films include a good step coverage, an excellent insulation, a good adhesion to metal, a low reactiveness to metal, an excellent passivation against contamination.
Examples of such metal films include Al, Ti, Pt, Mo, W, and alloys thereof. Examples of such insulation films include SiO
2
, PSG, SiO
2
—PSG, SiO
2
-plasma Si
3
N
4
, Al
2
O
3
, and polyimide.
In the multi-layer wiring structure, gold may be plated for a metal so as to decrease the wiring resistance and increase the resultant height. However, the gold plate does not have good adhesion to a CVD passivation film formed thereon. To solve this problem, it is necessary to improve the adhesion to the passivation film by, for example, forming a Ti layer between the gold plate and the passivation film.
Next, with reference to
FIGS. 3A
to
3
H, a fabrication method of a conventional semiconductor device having a multi-layer wiring structure will be described.
A metal film
2
is formed on a GaAs semiconductor substrate
1
(see FIG.
3
A). The metal film
2
is composed of an Au layer, a Pt layer, and a Ti layer that successively disposed as an upper layer, a middle layer, and a lower layer, respectively. The thicknesses of the Au layer, the Pt layer, and the Ti layer are 10,000 Å, 300 Å, and 500 Å, respectively. An under-resist
3
is formed on the metal film
2
by photo-etching process (see FIG.
3
B). The under-resist
3
is hard-baked (see FIG.
3
C). A plating base metal film
4
is formed on the hard-baked under-resist
3
. The plating base metal film
4
is composed of an Au layer and a Ti layer that are successively disposed as an upper layer and a lower layer, respectively (see FIG.
3
D). The thicknesses of the Au layer and the Ti layer are 1,000 Å and 50 Å, respectively. A top-resist
5
is formed by photo-etching process (see FIG.
3
E). A gold plate
6
is electrolytically precipitated to an area free of the top-resist
5
for a thickness of 4 &mgr;m (see FIG.
3
F). The top resist
5
and the under-resist
3
are successively peeled off (see FIG.
3
G). A Ti film
8
is evaporated or vapor deposited on the entire front surface of the substrate. The Ti film
8
is photo-etched with a mask. A resist
9
is peeled off (see FIG.
3
H). In the above-described steps, the Ti film
8
remains on the plating base metal film
4
in a whisker shape. In addition, it is difficult to form a CVD passivation film or the like on the Ti film
8
in such a manner that the CVD passivation film well covers bulky side walls of the gold plate.
As described above, in the semiconductor device having the multi-layer wiring structure, when gold is plated, a refractory metal such as Ti is evaporated so as to improve the adhesion of gold to the CVD passivation film. However, in this case, it is difficult to well cover the bulky side walls of the gold plate with the CVD passivation film.
SUMMARY OF THE INVENTION
This application claims priority on Japanese Patent Application No. Hei 10-176456 filed on Jun. 23, 1998, the contents of which are incorporated herein by reference.
An object of the present invention is to provide a semiconductor device having an inter-layer insulation film that allows a refractory metal to be easily etched and that well covers bulky side walls of a gold plate. Another object of the present invention is to provide a fabrication method of such a semiconductor device.
A first aspect of the present invention is a semiconductor device, at least comprising a semiconductor substrate, a conductive portion formed on the semiconductor substrate, a metal film formed on the conductive portion, a gold plate portion formed on the metal film, an inter-layer insulation film formed on an area of the semiconductor substrate, the area being free from the conductive portion, the metal film and the gold plate portion in such a manner that the inter-layer insulation film contacts side walls of the conductive portion, the metal film and the gold plate portion, a refractory metal film formed in such a manner that the refractory metal film coats the gold plate portion, and a protection film formed in such a manner that the protection film exposes part of the refractory metal film as an electrically connecting portion and coats the inter-layer insulation film and the refractory metal film.
A second aspect of the present invention is a fabrication method for a semiconductor device, at least comprising the steps of depositing a conductive film on a semiconductor substrate and patterning the conductive film to form a conductive portion, depositing a metal thin film on the conductive portion, forming a gold plate portion on the metal thin film, coating the semiconductor substrate, the conductive portion, the metal thin film, and the gold plate portion with an inter-layer insulation film, patterning the inter-layer insulation film in such a manner that only an upper portion of the gold plate portion is exposed, depositing a refractory metal film on the exposed gold plate portion, depositing a protection film on the inter-layer insulation film and the refractory metal film, and forming an opening in the protection film and exposing part of the refractory metal film as an electrically connecting portion.
In the semiconductor device and fabrication method thereof according to the present invention, since the inter-layer insulation film is disposed on the bulky side walls of the gold plate portion, improved coverage of the protection film formed thereon is achieved. In addition, after the inter-layer insulation film is deposited, the upper portion of the gold plate is exposed and the refractory metal is evaporated thereto. Thus, the refractory metal can be easily and accurately etched.
In the semiconductor device and fabrication method thereof according to the present invention, the material of the inter-layer insulation film is not limited as long as it can smoothly adhere to a thick film. Examples of the material of the inter-layer insulation film include organic resin films such as benzocyclobutene and polyimide.
The inter-layer insulation film is coated as a thick film with a thickness almost twice larger than the film thickness of the gold plate. Consequently, side walls of the gold plate are covered with the inter-layer insulation film, thereby forming the Ti film uniformly on the gold plate. Thus, the problem of the step coverage can be solved.
Benzocyclobutene has a structure shown in
FIG. 2
where R rep
Tomita Mayumi
Yasuda Hidefumi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Eddie C.
Lee Eugene
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