Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2009-01-16
2010-02-23
Luu, Chuong A. (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S615000, C257S065000, C257S900000
Reexamination Certificate
active
07667227
ABSTRACT:
A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
REFERENCES:
patent: 6221131 (2001-04-01), Behling et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 7262465 (2007-08-01), Hatada et al.
patent: 2003/0104645 (2003-06-01), Weon et al.
patent: 2005/0285203 (2005-12-01), Fukutome et al.
patent: 2006/0289856 (2006-12-01), Shimamune et al.
patent: 63-153863 (1988-06-01), None
patent: 2004-31753 (2004-01-01), None
Scott E. Thompson et al., A 90-nm Logic Technology Featuring Strained-Silicon, IEEE Transactions on Electron Devices, vol. 51, No. 11, pp. 1790-1797, Nov. 2004.
European Search Report dated Aug. 2, 2007 issued in corresponding Application No. 05007947.4-1235.
Loo R et al., “A New Technique To Fabricate Ultra-Shallow-Junctions, Combining In Situ Vapour HCI Etching and In Situ Doped Epitaxial SiGe Re-Growth”, Applied Surface Science, Elsevier, Amsterdam, NL, vol. 224, No. 1-4, Mar. 15, 2004, pp. 63-67.
Ghani T et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, International Electron Devices Meeting 2003. IEDM. Technical Digest. Washington, DC, Dec. 8-10, 2003, New York, NY, Dec. 8, 2003, pp. 978-980.
Matsuda T et al., “Electrical Characteristics Of Oo/+-45o/90o-Orientation CMOSFET WithSource/Drain Fabricated by Various Ion-Implantation Methods”, IEEE Transactions On Electron Devices, IEEE Service Center, Piscataway, NJ, US, vol. 46, No. 4 Apr. 1999, pp. 703-711.
Moroz V et al., “Analyzing Strained-Silicon Options For Stress-Engineering Transistors”, Solid State Technology, Pennwell Corporation, Tulsa, OK, US , vol. 47, No. 7, Jul. 2004, pp. 49-50, 52.
Japanese Office Action dated Jul. 15, 2008, issue in corresponding Japanese patent application No. 2004-380619.
Hatada Akiyoshi
Katakami Akira
Shima Masashi
Shimamune Yosuke
Tamura Naoyoshi
Fujitsu Microelectronics Limited
Luu Chuong A.
Westerman Hattori Daniels & Adrian LLP
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