Semiconductor device and fabrication method therefor

Details Semiconductor device and fabrication method therefor Semiconductor device and fabrication method therefor

2002-10-01

2003-12-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

On insulating substrate or layer

C438S162000, C438S407000, C438S775000

Reexamination Certificate

active

06664165

ABSTRACT:

TECHNICAL FIELD
This invention relates to a semiconductor apparatus in which a MOS transistor is formed in a device region separated by an isolation region and to a method of fabricating same. In particular, it relates to a novel method of suppressing the diffusion of impurities with respect to an insulation substrate at an end portion of an SOI active layer in an SOI-type semiconductor apparatus.
BACKGROUND ART
With the progress in the miniaturization of semiconductor integrated circuits in recent years, SOI (Silicon On Insulator) structures, in which the junction capacitance between a substrate and a junction section (junction) is reduced and power consumption is lowered by providing an insulator between a silicon substrate and a MOS transistor, is attracting attention. In such an SOI-type semiconductor apparatus, because isolation between the devices is performed with a silicon oxide layer as an insulation layer, even in an SOI-type semiconductor apparatus with a high degree of integration, soft errors and latch-ups can easily be suppressed, and a high reliability can be secured. Further, in an integrated circuit apparatus having an SOI structure, because the junction capacitance of an impurity diffusion layer in a device region can be reduced, charge and discharge currents which accompany switching becomes lower, and it becomes more advantageous in attempting to increase speed, and to lower power consumption.
In an SOI-type semiconductor apparatus, a process similar to that of forming a transistor on an ordinary bulk silicon wafer may be applied to the gate structure and wiring process or the like in forming a transistor in a device region. However, when performing isolation in an SOI-type semiconductor apparatus applying the conventionally well known LOCOS (Local Oxidation of Silicon) method, because field oxidation speed has pattern dependence, the following problems were present in employing a process applied to ordinary bulk silicon wafers.
Below, a conventional isolation method is described with reference to the drawings.
FIG. 6
is a sectional view of a semiconductor apparatus, which describes isolation for a conventional SOI-type semiconductor apparatus by the LOCOS method. A LOCOS oxide film
111
is formed through selective oxidation with a patterned nitride film as a mask. When the LOCOS oxide film reaches a buried oxide film in a narrow isolation region and oxidation is advanced until isolation is complete, in the LOCOS oxide film of a wide isolation region, as shown in
FIG. 6
, an SOI layer
112
is affected by oxidation due to a wraparound from a buried oxide film
113
and transforms to resemble a bird's beak at a portion
114
in contact with the isolation region.
115
is a silicon substrate. When the SOI layer
112
transforms, there was a problem in that stress deflection (stress) from the transformed portion
114
is facilitated, crystal defects are formed in the device region of the SOI layer
112
, bringing about a leakage between a source and a drain. Further, with the miniaturization of circuitry, as in ordinary bulk silicon wafers, the critical dimension loss at an end portion of the LOCOS becomes a problem.
Thus, as an isolation method for an SOI-type semiconductor device that mitigates the problem of stress in the LOCOS method or the problem of critical dimension loss, the STI (Shallow Trench Isolation) method and Mesa-type isolation technique are being favored.
FIG. 7
is a drawing illustrating the structure of a cross-section of an SOI-type semiconductor apparatus to which STI isolation is applied. In the STI isolation method, after an SOI layer
112
is processed to form an island-shaped device forming region, the isolation region is buried with an STI insulation film
116
, and the surface is planarized by chemical mechanical polishing (CMP). Subsequently, an isolation mask is removed.
117
is a gate oxide layer and
118
is a gate electrode. This STI isolation method is often applied to SOI-type semiconductor devices in which the SOI layer
112
is formed in a thickness of 50 nm or above.
FIG. 8
is a drawing illustrating the structure of a cross-section of an SOI-type semiconductor apparatus to which Mesa-type isolation is applied. In Mesa-type isolation techniques, an SOI layer
112
is processed to form a silicon island, and after a sidewall is oxidized, an isolation mask is removed. Subsequently, impurities are introduced, gate oxidation is performed, further proceeding to a process of forming a gate electrode
118
. Mesa-type isolation makes the isolation of a device region by merely performing an isolation process selectively on the SOI layer
112
possible, and is applied to SOI-type semiconductor apparatuses in which the SOI layer
112
is thin.
However, even if either of the separation methods illustrated in FIG.
7
and
FIG. 8
is applied, due to the effect of the impurities diffused in the SOI layer
112
diffusing into the buried oxide film
113
therebelow as well, the impurity concentration in the SOI active layer becomes lower. Further, in a portion
112
a
where the gate electrode is in contact with the SOI layer via a thermal oxide layer, because diffusion in a lateral direction and an oblique direction occurs as well, the concentration profile of the active layer changes and becomes uneven, and a parasitic MOSFET with a low threshold voltage is formed thereat. As a result, there is a problem in that a hump occurs in the sub-threshold characteristics of the entire transistor, and good turn-off characteristics cannot be obtained.
The object of this invention lies in the prevention of concentration reduction in the SOI layer in forming the MOSFET by applying Mesa-type isolation techniques or the STI isolation method, while at the same time providing an SOI structure semiconductor apparatus improved such that a parasitic MOSFET is not formed, and a method of fabricating same.
DISCLOSURE OF THE INVENTION
In order to attain the object above, there is provided a semiconductor apparatus in which a MOS transistor is formed in a device region separated by an isolation region. This semiconductor apparatus comprises an insulation substrate, a semiconductor layer formed in a device region on the insulation substrate mentioned above, an insulation layer formed so as to cover a sidewall surface of the insulation substrate mentioned above, and is characterized in that nitrogen atoms are introduced into a portion of the surface of the insulation substrate mentioned above and the insulation layer mentioned above.
Further, there may be provided a method of fabricating a semiconductor apparatus which forms a MOS transistor in a device region separated by an isolation region on an insulation substrate. This fabrication method for a semiconductor apparatus comprises a mask step for forming an isolation mask which removes a semiconductor layer from an isolation region of the semiconductor layer on the insulation substrate, a removal step for removing the semiconductor layer from the isolation region using the isolation mask mentioned above, a nitrogen introduction step for introducing nitrogen atoms into a portion in contact with a sidewall surface of the semiconductor layer in the device region or the semiconductor layer on the insulator substrate by performing a nitridation oxidation process on the insulation substrate mentioned above, a device forming step for introducing impurities into the semiconductor layer in the device region and forming an active layer region, and a gate creation step for forming an oxide layer and an electrode in the device region mentioned above.
According to the present invention, impurity diffusion with respect to the insulation substrate at an end portion of the SOI active layer in the SOI-type semiconductor device may be suppressed.


REFERENCES:
patent: 5972777 (1999-10-01), Hsu et al.
patent: 6225151 (2001-05-01), Gardner et al.
patent: 6229184 (2001-05-01), Riccobene
patent: 6528434 (2003-03-01), Chen
patent: 05-206421 (1993-08-01), None
patent: 07-273188 (1995-10-01), None
patent: 11-135615 (1999-05-01

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