Semiconductor device and dummy pattern arrangement method

Details Semiconductor device and dummy pattern arrangement method Semiconductor device and dummy pattern arrangement method

2009-12-07

2011-12-06

Whitmore, Stacy (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S658000

Reexamination Certificate

active

08072078

ABSTRACT:
A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern.

REFERENCES:
patent: 7675161 (2010-03-01), Hashimoto et al.
patent: 2000-277615 (2000-10-01), None
patent: 2002-368088 (2002-12-01), None
patent: 2003-140319 (2003-05-01), None
patent: 2004-253655 (2004-09-01), None

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