Semiconductor device and driving method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device

Reexamination Certificate

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C257S109000, C257S110000, C257S115000

Reexamination Certificate

active

06521918

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device with four-layer structure (PNPN structure) such as Gate Commutated Turn-off Thyristor (GCT).
BACKGROUND ART
Semiconductor devices for a large amount of electric power have been improved to deal with a high voltage and a large amount of current. A gate commutation thyristor element, for example, allows now a maximum current of 4000A driven by DC3000V to flow without any snubber circuit.
Turn-off operation of this gate commutated turn-off thyristor element (hereinafter referred to as GCT element) is conducted by applying a negative voltage to a gate electrode. All of the main current flowing from the anode to the cathode through the GCT element is then commutated instantaneously to a gate circuit through the gate electrode. This results in a quick formation of a depletion layer in a P-N junction between a gate and a cathode, which in turn prevents the injection of electrons from the cathode.
Subsequently, when there is no injection of electrons from the cathode, the thyristor operation of PNPN structure between the anode and the cathode switches over to the transistor operation of PNP structure between the anode and the cathode. This purposefully brings about a state where there is no bias between base and emitter of the PNP transistor. Consequently, a turn-off operation can be performed in the same manner as a bias free transistor operation.
FIG. 7
is a sectional view showing an arrangement of a conventional GCT element, for example.
FIG. 8
is a plan view of the GCT element in
FIG. 7
viewed from the cathode side.
FIG. 7
is a sectional view taken along the line A—A in FIG.
8
. In the drawings, reference numeral
101
is an N-type base region of a semiconductor substrate comprised of an N-type semiconductor, and numeral
102
is a P-type emitter region comprised of a P-type semiconductor formed on one side of the main face of the N-type base region
101
. Numeral
103
is a P-type base region comprised of a P-type semiconductor formed on the other side of the main face of the N-type base region
101
. Numeral
104
is the N-type emitter region comprised of an N-type semiconductor selectively formed on upper part of the P-type base region
103
.
Numeral
105
is a cathode electrode formed over the N-type emitter region
104
. Numeral
106
a
is a gate electrode formed over the parts surrounded by the N-type emitter
104
of the P-type base region
103
, and numeral
106
b
is a gate electrode formed to surround the N-type emitter
104
around the outer edge area of the P-type base region
103
. Numeral
107
is an anode electrode formed over the P-type emitter region
102
.
Turn-off operation of the GCT element indicated in
FIGS. 7 and 8
is hereinafter described. In its on state, the main current flows from the anode electrode
107
through the GCT element to the cathode electrode
105
. When switching over from this on state to an off state, a negative voltage is applied to the gate electrodes
106
a
and
106
b
to reduce an electric potential of the gate electrodes
106
a
and
106
b
to a level lower than the electric potential of the cathode electrode
105
. This results in all of the main current flowing through the cathode electrode
105
being commutated to the gate electrodes
106
a
and
106
b.
Additionally, as the P-N junction between the gate and the cathode becomes reverse biased, a depletion layer is formed quickly in the P-N junction between the gate and the cathode. As a result, no more electrons are injected from the cathode electrode
105
through the P-N junction.
In this manner, when there is no more injection of electrons from the cathode electrode
105
, the thyristor operation of the PNPN structure between the anode and the cathode, in which the current has been flowing through the P-type emitter region
102
, the N-type base region
101
, the P-type base region
103
and the N-type emitter region
104
, is switched over to a PNP transistor operation between the anode and the gate, in which the current flows through the P-type emitter region
102
, N-type base region
101
and the P-type base region
103
. At this point, there is no application of a bias voltage between the N-type base region
101
and the P-type base region
103
, and therefore vanishing of the carrier in the N-type base region
103
is not controlled from the outside. This results in an end of the turn-off state with the passage of time as the carrier continues to be vanished by repeated re-coupling.
FIG. 9
is a graph showing a current and a voltage between the anode and cathode of the conventional semiconductor device shown in FIG.
7
and FIG.
8
. In the drawings, axis of ordinates plots the current (A) and the voltage (V), and axis of abscissas plots the time (sec). As maybe seen in
FIG. 9
, when the main current is commutated from the cathode electrode
105
to the gate electrodes
106
a
and
106
b,
the current flowing between the anode and the cathode is rapidly reduced and eventually the flow of the current stops.
Further, as may be seen in
FIG. 9
, when the main current is commutated from the cathode electrode
105
to the gate electrodes
106
a
and
106
b
and the thyristor operation switches over to transistor operation, a depletion layer is formed in the P-N junction between the P-type base region
103
and the N-type base region
101
. And the voltage between the anode and the cathode increases in line with the spreading or extension of this depletion layer, and eventually the voltage between the anode and the cathode converges upon a predetermined voltage level.
In the case of the conventional semiconductor device shown in FIG.
7
and
FIG. 8
not arranged by burying the N-type emitter region in the P-type base region but arranged by forming the N-type emitter region on the P-type base region, when starting switching operation at a high speed, the current becomes concentrated locally or partially on the P-type base region between the gate electrode and the cathode electrode. This results in the possibility of element breakdown.
To cope with this disadvantage, the Japanese Patent publication (unexamined) No. 22608/1995 discloses a thyristor in which a P

region is established between the gate electrode and the cathode electrode, and an auxiliary gate electrode coated with an oxide layer is also provided on the P

region. During switch operation, the carrier particle density of the P

region is reduced by the auxiliary gate electrode, making it difficult for the controlling current to flow, which in turn prevents the current from being locally concentrated on the P-type base region.
The Japanese Patent publication (unexamined) No. 110068/1993 discloses a thyristor in which, in order to reduce the gate driving current in the PNPN thyristor equipped with a control gate at the time of turning off, a P-type base region and a P-type collector region are provided on the N-type base region with a predetermined distance from each other. Further, an N-type emitter region and a first cathode electrode are provided on the P-type base region, and a second cathode electrode is also provided on the mentioned P-type collector region. Furthermore, a new gate electrode coated with an oxide layer is formed between the first and second cathode electrodes. At the time of turning-off, a voltage is applied to the gate electrode to connect the P-type base region to the P-type collector region through a channel, so that the main current flowing between the anode and the cathode is switched over to the turn-off state.
However, the conventional semiconductor device arranged as mentioned above has following problems to be solved.
First, in the turning-off operation of the conventional semiconductor device of above arrangement, when commutating the main current from the cathode electrode to the gate electrode, thereby switching over from the thyristor operation to the transistor operation, there is no bias between the emitter and the base of the transistor in this transistor operation. Therefo

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