Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-11-28
2003-09-16
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S089000, C345S095000, C345S211000, C345S213000
Reexamination Certificate
active
06621478
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices for driving a display device with a display data signal which has been subjected to digital/analogue conversion to effect a tone display, and further relates to display modules incorporating such a semiconductor device.
BACKGROUND OF THE INVENTION
Popularly known, conventional liquid crystal display devices include those using TFTs (thin film transistors) shown in
FIG. 11
, which is a typical active matrix addressing method. The liquid crystal display device is constituted by: a TFT liquid crystal panel
901
as a liquid crystal display section; and a liquid crystal drive device. Inside the liquid crystal panel
901
, there are provided liquid crystal display elements (not shown) and opposite electrodes (common electrodes)
906
.
The liquid crystal drive device includes source drivers
902
, gate drivers
903
, a controller
904
, and a liquid-crystal-drive power source
905
. The source and gate drivers
902
and
903
each include an integrated circuit. The controller
904
provides display data D and a control signal S
11
to the source drivers
902
and a control signal S
12
to the gate drivers
903
. The control signal S
11
may be a horizontally synchronized signal or a clock signal, for example. The control signal S
12
may be a vertically synchronized signal, for example.
The output terminal for a liquid-crystal-drive voltage of each source driver
902
is coupled to an associated source signal line of the liquid crystal panel
901
. The output terminal for a liquid-crystal-drive voltage of each gate driver
903
is coupled to an associated gate signal line of the liquid crystal panel
901
. The liquid-crystal-drive power source
905
supplies power to drive the liquid crystal drive devices (source and gate drivers
902
and
903
) and also provides various drive voltages which will be applied to the liquid crystal panel
901
.
The digital display data D is externally provided in a serial data format to the controller
904
and then transmitted to the source drivers
902
. Each source driver
902
latches the incoming display data D as a time series and converts it from serial to parallel, before performing digital-to-analogue conversion (hereinafter, D/A conversion) on the display data D in synchronism with the horizontally synchronized signal supplied from the controller
904
. The analogue display data D is then fed as a display signal from the source driver
902
. The display signal contains an analogue voltage (tone display voltage) to effect a tone display.
Supplied from the source driver
902
through its output terminal for a liquid-crystal-drive voltage, the D/A converted display signal is transmitted via the source signal line to an associated liquid crystal display element (not shown) in the liquid crystal panel
901
.
FIG. 12
shows, as an example, a block diagram of a circuit structure of the source driver
902
. The source driver
902
is primarily constituted by a shift register circuit
1302
, an input latch circuit
1301
, a sampling memory circuit
1303
, a hold memory circuit
1304
, a level shifter circuit
1305
, a D/A conversion circuit
1306
, an output circuit
1307
, and a reference voltage generating circuit
1309
.
The shift register circuit
1302
includes shift registers with n stages. A start pulse signal SP in synchronism with the horizontally synchronized signal is supplied to the first stage in the shift register circuit
1302
and subsequently passed on from one stage to a next in synchronism with a clock signal CK until it reaches the n-th stage in the shift register circuit
1302
.
The output of the n-th stage in the shift register circuit
1302
, designated as an output signal SPO, is supplied as a start pulse signal SP to a next source driver
902
(the source drivers
902
are connected in cascade). The start pulse signal SP is passed on from a source driver
902
to another.
The display data D is composed of, for example, three kinds of 6-bit display data DR (red), DG (green), and DB (blue), and is provided to the input latch circuit
1301
, where it is latched temporarily before being fed to the sampling memory circuit
1303
according to the clock signal CK. The sampling memory circuit
1303
performs sampling and stores the incoming time-series (serial) display data D according to the output signal from various stages in the shift register circuit
1302
(the signal derived by shifting the start pulse signal SP).
The display data D is then supplied to the hold memory circuit
1304
, where the display data D is latched according to a latch signal LS derived from the horizontally synchronized signal when part of the display data D for a single horizontal period is fed to the hold memory circuit
1304
. The hold memory circuit
1304
then holds the display data D until it receives a next latch signal LS, that is, for one horizontal period, before sending out the display data D.
The levels of signals representative of the latched display data D are changed by the level shifter circuit
1305
from voltage levels as logic representations (Vcc-GND levels) to those required to drive the liquid crystal (VDD-GND levels).
Meanwhile, the reference voltage generating circuit
1309
produces, for example, 64 different levels of voltages, based on reference voltages VR (including, for example, Vref
1
to Vref
9
), which will be used to effect a tone display using a potential dividing or another technique. The D/A conversion circuit
1306
converts to analogue voltages by selecting one of the 64 voltage levels according to the incoming display data D composed of the aforementioned three kinds of 6-bit display data DR, DG, and DB, which have been latched and changed in levels. The D/A conversion circuit
1306
then outputs the results as display signals.
These display signals having various voltage levels are fed as tone display voltages from the output circuit
1307
which includes a voltage follower circuit via the output terminals
1308
for liquid-crystal-drive voltages to source signal lines of a liquid crystal display element in the liquid crystal panel
901
.
As illustrated in
FIG. 12
(only a single circuit is shown) and in
FIG. 13
, external serial inputs (D
1
, D
2
, . . . D
8
, . . . ) of digital display data (DR, DG, and DB) received by the conventional-source driver described above is latched temporarily by the input latch circuit
1301
constituted by a D-type flip-flop (hereinafter, a DF/F) at the leading edge of the clock signal CK (see the data-latching timing chart in FIGS.
14
(
a
) through
14
(
c
)).
Subsequently to this, the latched display data D is supplied to the sampling memory circuit
1303
constituted by a DF/F, where it is synchronized the leading edge of output signals (SR
1
, SR
2
, . . . SRn) and stored. The output signals (SR
1
, SR
2
, . . . SRn) are provided by the n stages in the shift register circuit
1302
as results of the transmission of the start pulse signal SP through these n stages at the leading edge of the clock signal CK. The display data D is subsequently supplied to the hold memory circuit
1304
and then provided as output signals by the hold memory circuit
1304
according to the latch signal LS, so that the hold memory circuit
1304
can hold the output signals until it receives a next latch signal LS.
However, in this conventional case, an attempt to improve the resolution of the liquid crystal panel
901
to eventually achieve an improvement in the quality of displayed images inevitably leads to degradation of the quality of displayed images. Specifically, in a case when the liquid crystal panel
901
is a conventional SXGA (Super extended Graphics Array; 1024×RGB×768) which requires
18
sets of RGB-compatible display data D (6 bits×RGB), as an example, the source driver
902
, for example, needs to transfer the display data D at an extremely high data transfer rate of 65 MHz which would be derived from the clock signal CK, so as to effect a 64 tone display.
Therefore, in the conventional
Ogawa Yoshinori
Sakaguchi Nobuhisa
Dharia Prabodh
Mengistu Amare
Sharp Kabushiki Kaisha
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