Semiconductor device and data processor

Details Semiconductor device and data processor Semiconductor device and data processor

2008-12-23

2010-10-19

Geyer, Scott B (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Miscellaneous

Reexamination Certificate

active

07816795

ABSTRACT:
Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.

REFERENCES:
patent: 2007-213375 (2007-08-01), None

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