Semiconductor device and a process for producing same

Details Semiconductor device and a process for producing same Semiconductor device and a process for producing same

2003-05-21

2004-06-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including diode

C257S577000, C257S547000, C257S372000

Reexamination Certificate

active

06756280

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a bipolar transistor and a process for producing the same, and more particularly to a semiconductor device, in which a (planar) junction type diode is constructed by using impurity regions of a vertical npn bipolar transistor, a horizontal pnp bipolar transistor, and an electrode wiring, and a process for producing the same.
BACKGROUND OF THE INVENTION
FIG. 1
shows a structure of a semiconductor device of a planar junction type diode using a vertical npn bipolar transistor.
In the semiconductor device having a vertical npn bipolar transistor, an n type high concentration collector buried region (N-BL; N-buried layer)
209
is constructed in a p type semiconductor substrate (P-sub)
206
, and an ISO
208
called a channel stopper is constructed in an outer periphery thereof by p type high concentration diffusion in the vertical direction, so that the elements are physically or electrically isolated.
On an upper part of the channel stopper of the p type high concentration impurity region ISO
208
, an insulating layer constructed with a silicon oxide film (or an element isolating region, LOCOS; local oxidation of silicon)
207
is further formed. In the region surrounded by the LOCOS
207
, elements, such as a transistor, are formed.
On an upper part of the n type high concentration collector buried region
209
, an n type epi layer (n type epitaxial layer, or an N-epi layer)
202
is constructed, which is formed by epitaxial growth.
In the n type epitaxial layer
202
, a p type intrinsic base region (described as an intrinsic base region or simply as a base region)
201
is constructed. Inside the intrinsic base region
201
, an n type high concentration emitter region
203
, in which an n type impurity is diffused, is constructed.
Next, on the both ends of the collector buried region
209
to the surface of the epitaxial layer
202
, an N
+
sinker (PLG; plug)
205
of a high concentration of an n type impurity is constructed to decrease the collector resistance.
Furthermore, over the whole upper surface of the p type semiconductor substrate
206
, insulating films
212
and
213
comprising SiO
2
are accumulated, with electrode windows for the emitter region
203
, base region
201
and N
+
sinker
205
constituting a part of collector region being opened, respectively.
On an upper part of the N
+
sinker
205
for withdrawing the collector electrode, a metallic electrode film, such as Al, is accumulated along with a base metallic electrode film (sometimes simply referred to as a base electrode)
210
and an emitter metallic electrode film (sometimes simply referred to as an emitter electrode)
214
, to constitute a collector metallic electrode film (sometimes simply referred to as a collector electrode)
215
. An interlevel insulating film, an upper layer wiring layer are formed on an upper part of the metallic electrode film to constitute an integrated circuit.
As an example using as a circuit where a planar junction type diode is constructed by using the vertical npn bipolar transistor described above, as shown in
FIG. 1
, a constant bias voltage Vf is applied to the base metallic electrode film
210
, the emitter metallic electrode film
214
is made open, and the collector metallic electrode film
215
is connected to the circuit, so as to realize a diode using the base/collector electrodes.
A specific example of an equivalent circuit of the diode constructed by the structure is shown in FIG.
2
.
In order to reduce the influence of the parasitic pnp bipolar transistor, as shown in
FIG. 1
, the P-sub
206
is separated by the collector buried region (N-BL)
209
and the N
+
sinker (PLG)
205
of the collector electrode withdrawing region, but it is not sufficient thereby.
The results thereof are shown in FIG.
3
. The abscissa is the applied voltage supplied to the base electrode
210
(sometimes referred to as a bias voltage) Vf, which is graduated from 20.5 V to 22.5V by a step of 0.5 V, and the ordinate indicates the electric current Ic flowing in the collector electrode
215
and the leakage electric current Isub flowing in the P-sub
206
, which is graduated in a logarithmic scale in the range of from 0.01 &mgr;A to 100 &mgr;A.
As shown in FIG.
1
and
FIG. 2
, however, in the related art planar PN junction type diode using the base/collector junction of the vertical npn bipolar transistor, in the case where the bias voltage is applied to the normal direction, a parasitic pnp bipolar transistor generated between an N-epi layer
202
forming the base region (
201
) to the collector region of the transistor and the N-BL
209
to the P-sub (
206
) functions, and thus a leakage electric current (Isub) flowing (leaking) toward the P-sub (
206
) is generated.
In particular, in the case where trimming with a large electric potential difference between the base region (
201
) and the P-sub (
206
) (zapping voltage≅Bvbso) is conducted, the necessary electric current must flow in the normal direction on the Zener zap diode. At this time, a leakage electric current flowing toward the P-sub
206
is generated, and the possibility of forming latch up due to the leakage electric current is increased. The consuming electric power also becomes large as a matter of course.
When the applied voltage Vf supplied to the base electrode of the vertical npn transistor is 21.0 V, the collector electric current Ic is about 1.5 &mgr;A, and the leakage electric current Isub is 4.5 &mgr;A, i.e., the leakage electric current is larger. When the applied voltage Vf becomes 21.5 V, Ic is 18 &mgr;A, and Isub is 30 &mgr;A, i.e., Isub is larger. Furthermore, when the applied voltage Vf becomes 22 V, Ic and Isub are substantially the same, which are about 40 &mgr;A.
As described herein, in the junction type diode having the structure shown in
FIG. 1
, the leakage electric current Isub flowing in the P-sub
206
is equivalent to or larger than the electric current Ic flowing in the diode, and thus the leakage electric current is large. That is, the necessary potential difference required for zapping to the Zener zap diode cannot be obtained, and the zapping cannot be certainly conducted. In order to reduce the influence (h
FE
) of the parasitic pnp transistor, the collector ring structure is employed, as shown in
FIG. 1
, in which the gap between the p type substrate and the collector is surrounded by the high concentration n
+
layer by using the n type buried layer (N-BL)
209
and the collector electric current withdrawing (plug) layer
205
, but it cannot be sufficient countermeasure.
SUMMARY OF THE INVENTION
The invention relates to a semiconductor device and a process for producing the same, by which the problems associated with the conventional techniques are solved.
A first semiconductor device is equipped with a trimming circuit having a Zener zap diode, the semiconductor device comprising a diode between a terminal for applying a voltage used on trimming the trimming circuit and the Zener zap diode, the diode comprising a first region of a first conductive type and a second region of a second conductive type formed on a substrate, the diode further comprising a third region of the second conductive type in at least a part of the first region, the third region being separated from the second region by the first region, and the third region being connected to the first region with wiring.
The first semiconductor device has a pn junction diode using a base/collector junction of an npn transistor, and by connecting the emitter (the third region) and the base (the first region) by wiring (EB short), the npn transistor is operated in reverse, to increase the collector electric current (Ic). By such a manner, the ratio of Ic becomes large with respect to the leakage electric current (Isub) leaking to the side of the p type substrate. As a result, when the Ic is constant, the leakage electric current (Isub) leaking to the side of the p type substrate is decreased. When the comp

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