Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-07-13
2003-06-24
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S666000
Reexamination Certificate
active
06583511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technology effective for tendencies toward high capacities and thin bodies of semiconductor devices.
2. Discussion of Background
In accordance with a tendency of high capacities of memory ICs in accordance with a tendency of a variety of functions of electronic equipments, a semiconductor device, called Multi Chip Package (MCP), which is formed by two semiconductor chips sealed by a sealing material, is developed.
FIG. 10
is a cross-sectional view in a process of wire bonding for manufacturing a conventional MCP, disclosed in Japanese Unexamined Patent Publication JP-A8-181165. To one surface, i.e. an active surface
1
b
, downward positioned in
FIG. 10
, of a double-sided semiconductor chip
1
having an active surface
1
a
and the active surface
1
b,
a single surface
2
a
of an inner lead, upward positioned in
FIG. 10
, is fixed by a bonding material
3
. One end of an Au wire
4
is connected to pads (not shown), formed on the active surface
1
a
and the active surface
1
b,
by a ball bond
4
c
. The other end of the Au wire is connected to the one side
2
a
of the inner lead and the other side
2
b
of the inner lead by a stitch bond
4
d.
This wire bonding method is called a forward wire bonding method, by which the wire is subjected to ball bonding to a pad on a semiconductor chip and to stitch bonding to a lead frame.
FIG. 10
is a cross-sectional view in a stage before a process of sealing by a sealing resin. In order to cover a top end portion of the Au wire
4
to seal by the sealing resin, a height A of the top end portion of the Au wire upward extended from the active surface
1
a,
a thickness B of the double-sided semiconductor chip
1
, and a dimension A to a top end portion of the Au wire downward extended from the active surface
1
b
determine a thickness as a sum, i.e. A+B+A, under a state that MCP is sealed.
Further, in the conventional semiconductor device, a step is formed in the inner lead
2
so as to reduce a difference between heights of the ball bond
4
c
and the stitch bond
4
d
in order to prevent a contact between the Au wire
4
and an outer periphery of the semiconductor chip
1
.
However, in the above-described conventional semiconductor device, the step of the inner lead is formed by bending. Therefore, a tolerance of ±10 &mgr;m exists in the step of the inner lead, formed at a time of mass production. On the other hand, the inner lead
2
is deformed as much as an actual tolerance between the jig and the inner lead when the inner lead
2
is tightened and fixed for wire bonding by a supporting jig machined to have predetermined dimensions and a lead securing jig
6
machined to have predetermined dimensions. When the wire bond is completed and the securing jigs are removed, the inner lead shows a returning motion by an amount of a forcible displacement of the inner lead. By this motion of the inner lead, fixed ends of the Au wire
4
, already wire bonded, namely the ball bond
4
c
and the stitch bond
4
d
, are displaced, whereby a quality in the wire bonding process becomes unstable.
Further, a dimension of the step of the inner lead having the bending tolerance makes the quality and the sealing process unstable because a cross-sectional area of a flow path of a resin is changed.
On the other hand, by providing the ball bond
4
c
in the pad positioned on the active surface
1
b
and the stitch bond in the inner lead
2
b,
it is impossible to make the thickness after sealing thin because even though a step having a dimension C, obtained by adding the plate thickness of the inner lead
2
to the thickness of the bonding material
3
, is provided between the ball bond and the stitch bond, the inner lead is formed on one of the surfaces, i.e. the active surface, of the double-sided semiconductor chip, and is subjected to the forward wire bonding in the pad, the total thickness of the semiconductor (MCP) depends on the sum A+B+A, of the height A of the loop, upward extended from the active surface
1
a,
the thickness B of the double-sided semiconductor chip
1
, and the dimension A of the loop of the Au wire, downward extended from the active surface
1
b.
Further, the supporting jig
5
used for wire bonding does not deform the two surfaces having the steps and the Au wire
4
by simultaneously supporting two surfaces of the back surfaces
2
b
of the inner lead
2
, bent to have the two steps, as illustrated in FIG.
10
. Therefore, a third recess is further required to prevent a contact of the Au wire
4
, downward protruded by the dimension D from the back surface
2
b
of the inner lead
2
. Accordingly, it is necessary to prepare the supporting jig
5
having three step surfaces, and, it is technically difficult to process the two surfaces having the steps so as to simultaneously support the two back surfaces
2
b
of the inner lead
2
, having the tolerances, whereby such a process is complicated and increases a cost.
Further, when forward wire bonding is conducted, it is impossible to make the double-sided semiconductor chip without using a semiconductor chip of a center pad arrangement, of which pad is arranged in a center of an active surface, and a semiconductor chip of a peripheral pad arrangement, of which pad is arranged in a periphery of the active surface. Therefore, it is impossible to make a double-sided semiconductor chip achieving a requirement that MCP is fabricated by two memory semiconductor chips so as to double a memory capacity.
Further, in order to fabricate MCP using two memory semiconductor chips to double a memory capacity, Japanese Unexamined Patent Publication JP-A-11-163255 discloses that a Lead On Chip (LOC) structure, formed by fixing two sheets of frames to two active surfaces, is adapted, Au wires are subjected to forward wire bonding between pads and corresponding inner leads, and an entirety is covered by a sealing resin.
In this case, as long as the forward wire bonding is adapted, the thickness of an entire MCP is resultantly a sum A+B+A of a height A of a loop of the Au wire, upwardly extended from the active surface
1
a,
the thickness B of the double-sided semiconductor chip
1
, and a dimension A of a loop of the Au wire, downwardly extended from the active surface
1
b,
whereby it is impossible to reduce the thickness of the MCP in a similar manner to that in Japanese Unexamined Patent Publication JP-A-8-181165.
Further, because two sets of LOC structures, formed by joining an inner lead by a joining agent, are prepared on the active surfaces of the semiconductor chip, two expensive frames are required. Further, in a manufacturing process of integrating the two sets of LOC are bonded back to back, it becomes necessary to add accurate welding for bonding the two sheets of the lead frames with a high accuracy and fixing each other, whereby there is a drawback that a production cost is further increased.
SUMMARY OF THE INVENTION
An object of the present invention to provide a semiconductor device having a thin body by solving the deficiencies of the conventional semiconductor device.
Another object of the present invention is to provide a semiconductor device having a thin body at a low cost.
Another object of the present invention is to provide a method of manufacturing a semiconductor device having a thin body at a low cost with a higher quality.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a laminated semiconductor chip including a first semiconductor chip and a second semiconductor chip, respectively having a principle surface being active surfaces having pads and a back surface, which is laminated by fixing the back surface of the first semiconductor chip to the back surface of the second semiconductor chip by a first joining material;
a lead frame integrally formed out of a sheet of a flat plate so as to have an inner lead and an outer lead;
a second joining material;
metallic wires; and
a sea
Akiyama Tatsuhiko
Michii Kazunari
Dang Phuc T.
Ho Hoai
Leydig , Voit & Mayer, Ltd.
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