Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-12-27
2001-12-04
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C365S185110, C257S316000
Reexamination Certificate
active
06327182
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to semiconductor devices, and more particularly, to semiconductor devices having memory cells and methods of operating the memory cells.
RELATED ART
Floating gate memory cells are used in many semiconductor devices. The two most common memory architectures for floating gate memory arrays are NAND-type and NOR-type.
FIG. 1
includes a circuit schematic drawing of a portion of a floating gate memory array
15
having a NAND-type architecture. The word lines
19
form rows, and the memory cells
17
are connected in series along a column for a byte or word of data. The drain of a memory cell
17
is connected to the source of a different memory cell
17
. For a set of memory cells
17
corresponding to a byte or a word of data, only one drain for those memory cells
17
is connected to a drain bit line.
FIG. 2
includes a circuit schematic drawing of a portion of a floating gate memory array
10
having a NOR-type architecture. The control gates lie along a row of memory cells and are connected by a word line
12
. Four memory cells are illustrated in FIG.
1
. Unlike the NAND-type architecture, the memory cells
11
along each column are connected in parallel for a byte or word of data. The memory cells
11
have sources that are connected to a dedicated to a source bit line
13
and drains that are connected to dedicated drain bit lines
14
. As used in this specification, a dedicated bit line is a bit line that is connected to only one row or one column of memory cells.
FIG. 3
includes a plan view of one embodiment of the memory array illustrated in FIG.
2
. The layout illustrated in
FIG. 3
has active regions
30
that are surrounded by field isolation regions
31
. Although most of the active regions
30
are formed as strips, there are flags extending outward underneath the boxed Xs illustrated in FIG.
3
. Therefore, for the left hand active region
30
near the upper left-hand side of
FIG. 3
, a portion of the active region
30
extends to the right to underlie the drain bit line
14
closer to the left-hand side of FIG.
3
. The active region
30
continues down
FIG. 3
until about the middle of the figure and then extends out with another flag but this time to the left underneath the boxed Xs for the source bit line
13
that is closer to the left-hand side of FIG.
3
. The active region
30
continues down and has yet another flag extending to the right again underneath the drain bit line
14
closer to the left-hand side of FIG.
3
. The other active region
30
(closer to the right-hand side of
FIG. 3
) has a similar pattern.
Floating gates
122
overlie the active regions
30
and are covered by the word lines
12
that include control gates. After the formation of the word lines
12
, the dedicated source bit lines
13
and drain bit lines
14
are formed at the same feature level (i.e., metal
1
, etc.). A minimum space
34
lies between the dedicated source bit line
13
and drain bit line
14
within a memory cell, and another minimum metal space
32
lies between dedicated source bit line
13
and drain bit line
14
of different memory cells. The ability to shrink this cell is greatly limited by these space dimensions because all the dedicated source bit lines and drain bit lines are formed at the same feature level.
Different methods can be used to program the memory cells in memory arrays
15
and
10
of
FIGS. 1 and 2
, respectively. Each of the memory cells
17
in the NAND-type memory array
15
of
FIG. 1
can be programming using Fowler-Nordheim tunneling. In one programming method, the source, drain, and well regions are typically taken to approximately −5 volts and the control gate is taken to approximately +10 volts. As used in this specification, uniform channel biasing means that the source, drain, and well regions are at the same potential during an operation, such as programming.
A floating gate memory cell in a NOR-type architecture can be programmed by hot carrier (electron) injection or Fowler-Nordheim tunneling. With Fowler-Nordheim tunneling, typically only one of the source or drain regions for a memory cell is biased. Therefore, just like hot electron injection, most of the carriers pass to or from the floating gate through a relatively small area where the floating overlaps the source region or the drain region. Uniform channel biasing during programming, such as that used for NAND-type architectures, typically causes write disturb problems in NOR-type architectures, particularly those having bit lines shared between adjacent columns of memory cells.
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Atsushi Nozoe et al., “A 3.3V High-Density AND Flash Memory with 1 ms/512B Erase & Program Time”, Paper TA 7.3, 1995 IEEE International Solid State Circuits Conference, Flash Memory, pp. 124-125.
Burnett James David
Buxo Juan
Hansen John P.
Krueger Scott W.
Salter Eric Johan
Ho Hoai V.
Motorola Inc.
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