Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-07-15
2004-02-03
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S777000, C257S686000, C257S676000
Reexamination Certificate
active
06686663
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and to a technique for manufacturing the same; and, more particularly, the invention relates to a technique which is effective when applied to a semiconductor device having a plurality of semiconductor chips stacked therein, and which is resin-sealed in a single package.
BACKGROUND OF THE INVENTION
As one of the measures for increasing the capacity of a memory LSI, such as a flash memory or a DRAM (dynamic random access memory), a variety of memory module structures, which are manufactured by stacking semiconductor chips, each having such a memory LSI formed thereon, and then sealing them in a single package, have been proposed.
For example, Japanese Patent Application Laid-Open No. Hei 4(1992)-302164 discloses a package structure obtained by stacking, stepwise, in one package, a plurality of semiconductor chips having the same function and the same size via an insulating layer, and electrically connecting a bonding pad which is exposed at the stepped portion of each of the semiconductor chips with an inner lead of the package through a wire.
Japanese Patent Application Laid-Open No. Hei 11(1999)-204720 discloses a package structure manufactured by loading a first semiconductor chip on an insulating substrate via a thermocompressive sheet, loading on the first semiconductor chip a second semiconductor chip which is smaller in external size than the first semiconductor chip via another thermocompressive sheet, electrically connecting each of the bonding pads of the first and second semiconductor chips with an interconnect layer on the insulating substrate via a wire, and then resin-sealing the first and second semiconductor chips and the wire.
SUMMARY OF THE INVENTION
If at least two semiconductor chips, which are similar in size and in the position of a bonding pad thereof, are mounted, and the bonding pad of each of the semiconductor chips is connected with an electrode of the substrate by a wire, it becomes difficult to detect the existence of a short circuit between the wires in a visual inspection step conducted after completion of the wire bonding step, because a plurality of wires for connecting each of the electrically common bonding pads of these semiconductor chips with an electrode seem to overlap when viewed downwards from above.
Among the plurality of wires for connecting the electrically common bonding pad with an electrode, the wire to be connected with the bonding pad of the lower semiconductor chip lies almost directly under the wire to be connected with the bonding pad of the upper semiconductor chip. Lowering the loop height of the wire to be connected with the bonding pad of the upper semiconductor chip therefore reduces the distance between the wire and a wire directly thereunder, which tends to cause a short circuit between these wires. An increase in the loop height of the wire to be connected with the bonding pad of the upper semiconductor chip to prevent such a phenomenon, on the other hand, thickens the resin provided for sealing the semiconductor chip and wire, thereby making it difficult to reduce the thickness of the package.
An object of the present invention is to provide a technique for improving the reliability of the visual inspection conducted after a wire bonding step, in a semiconductor device having a plurality of semiconductor chips stacked on one another and sealed with a resin.
Another object of the present invention is to provide a technique for promoting a size and thickness reduction of a semiconductor device having a plurality of semiconductor chips stacked on one another and sealed with a resin.
A further object of the present invention is to provide a technique for reducing the manufacturing cost of a semiconductor device having a plurality of semiconductor chips stacked on one another and sealed with a resin.
The above-described and other objects and novel features of the present invention will be apparent from the description herein and the accompanying drawings.
Among the features of the invention disclosed by the present application, summaries of the typical aspects will next be described briefly.
A semiconductor device according to the present invention is obtained by mounting, over a substrate, a first semiconductor chip having a plurality of bonding pads formed along one of the sides of the main surface thereof; stacking, over the main surface of the first semiconductor chip, a second semiconductor chip having a plurality of bonding pads formed along one of the sides of the main surface thereof; electrically connecting each of the bonding pads of the first semiconductor chip and each of the bonding pads of the second semiconductor chip with an electrode on the substrate via a wire; and sealing the first and second semiconductor chips and the wires with a resin, wherein the second semiconductor chip is stacked over the main surface of the first semiconductor chip while being slid (i.e., offset) in a direction parallel to said one side of the semiconductor chip and in a direction perpendicular thereto.
Another semiconductor device according to the present invention is obtained by mounting, over a substrate, a first semiconductor chip having a plurality of bonding pads formed along one of the sides of the main surface thereof; stacking, over the main surface of the first semiconductor chip, a second semiconductor chip having a plurality of bonding pads formed along one of the sides of the main surface, while sliding (i.e., offsetting) the second semiconductor chip in a direction parallel to said one side of the first semiconductor chip and in a direction perpendicular thereto in such a way that the one side of the second semiconductor chip becomes opposite to the one side of the first semiconductor chip and the bonding pad of the first semiconductor chip is exposed; stacking a third semiconductor chip having a plurality of bonding pads formed along the one side of the main surface over the main surface of the second semiconductor chip in such a way that the one side of the third semiconductor chip extends along the same direction with the one side of the first semiconductor chip, and, at the same time, the third semiconductor chip is stacked to have the same direction with that of the first semiconductor chip; electrically connecting the bonding pads of the first, second and third semiconductor chips with electrodes on the substrate via wires; and sealing the first, second and third semiconductor chips and the wires with a resin.
The manufacturing process of the semiconductor device according to the present invention has the following steps:
(a) mounting, over a substrate, a first semiconductor chip having a plurality of bonding pads formed along one of the sides of the main surface;
(b) stacking, over the main surface of the first semiconductor chip, a second semiconductor chip having a plurality of bonding pads formed along one of the sides of the main surface, while sliding it in a direction parallel to said one side of the first semiconductor chip and in a direction perpendicular thereto;
(c) electrically connecting, via wires, the plurality of bonding pads formed on the first and second semiconductor chips with electrodes formed on the substrate; and
(d) sealing the first and second semiconductor chips and the wires with a resin.
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patent: 4-199566 (1992-07-01), None
patent: 4-302164 (1992-10-01), None
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Nishizawa et al. (US patent publication Application Publication US 2001/0009505) US class : 361/737.
Masuda Masachika
Usami Toshihiko
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nelms David
Nguyen Thinh T.
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