Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-10-16
2003-06-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S127000
Reexamination Certificate
active
06576498
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a technology for manufacturing the same, and particularly to a technology effective for application to a semiconductor device wherein two semiconductor chips are laminated and sealed with a resin.
A resin encapsulation type semiconductor device aimed at implementing each semiconductor chip in high density, in which a memory LSI such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory) or the like is formed, has been described in Japanese Patent Application Laid-Open No. Hei 7 (1995)-58281.
The resin encapsulation type semiconductor device described in the publication comprises an SOJ (Small Outline J-leaded) type package. In the semiconductor device, two semiconductor chips in which memory LSIs each having the same storage capacity are formed, are encapsulated inside a resin encapsulator formed by a transfer mold method, in a state in which they are laminated up and down.
The two semiconductor chips are placed in such a manner that their element forming surfaces are opposed to each other. Inner lead portions of a plurality of leads are placed on their corresponding circuit forming surfaces with insulating films interposed therebetween. Namely, the present resin encapsulation type semiconductor device is comprised of an LOC (Lead On Chip) structure wherein inner lead portions are placed on a circuit forming surface of each semiconductor chip. The respective inner lead portions are electrically connected to their corresponding bonding pads of each semiconductor chip through wires.
One of the two semiconductor chips is resin-encapsulated in a state of being fixed to leads of a first lead frame, whereas the other thereof is resin-encapsulated in a state of being fixed to leads of a second lead frame. Namely, the resin encapsulation type semiconductor device is manufactured by the two lead frames.
The inner lead portions of the leads connected to one of the two semiconductor chips, and the inner lead portions of the leads connected to the other thereof are bent in the direction in which they approach each other inside the resin encapsulator. Further, they are weld-bonded to one another by laser. The other ends of the leads connected to one semiconductor chip, of these leads are drawn outside from the sides of the resin encapsulator and constitute outer lead portions. On the other hand, since the other ends of the leads connected to the other semiconductor chip are subjected to the weld bonding process by the laser and thereafter cut off inside the resin encapsulator prior to a transfer mold process, they are not drawn outside the resin encapsulator. Namely, the outer lead portions drawn from the resin encapsulator constitute external connecting terminals common to the two semiconductor chips.
Incidentally, the present inventors have examined the references known to date after the completion of the present invention. As a result, the present inventors have further found Japanese Patent Application Laid-Open Nos. Hei 5(1993)-82719 and 10(1998)-506226 as prior arts other than the above, each of which relates to a semiconductor device wherein two semiconductor chips are laminated and encapsulated inside a resin encapsulator. However, a lead frame structure employed in a semiconductor device of the present invention to be described later in detail has not been described even in both of these publications.
SUMMARY OF THE INVENTION
Since the SOJ type package described in Japanese Patent Application Laid-Open No. Hei 7(1995)-58281, wherein the first semiconductor chip fixed to the leads of the first lead frame and the second semiconductor chip fixed to the leads of the second lead frame are laminated and sealed with the resin, makes use of the two lead frames, the number of members increases as compared with the normal SOJ type package using one lead frame, and the manufacturing cost of the package increases correspondingly.
Further, since the SOJ type package adopts the LOC structure wherein the inner lead portions of the first lead frame are placed on the circuit forming surface of the first semiconductor chip, and the inner lead portions of the second lead frame are placed on the circuit forming surface of the second semiconductor chip, it is difficult to reduce the thickness of the resin encapsulator in the direction in which the semiconductor chips are laminated.
An object of the present invention is to provide a technology for reducing the manufacturing cost of a semiconductor device wherein two semiconductor chips are stacked on each other and sealed with a resin.
Another object of the present invention is to provide a technology for promoting a reduction in the thickness of a semiconductor device wherein two semiconductor chips are laminated and sealed with a resin.
The above, and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
There is provided a semiconductor device according to the present invention, which comprises first and second semiconductor chips laminated so as to oppose backs thereof to each other, fixed potential leads placed in the vicinity of sides of the first and second semiconductor chips, a plurality of signal leads, a plurality of bonding pads formed over a main surface of the first semiconductor chip, a plurality of bonding pads formed over a main surface of the second semiconductor chip, and a plurality of wires, and wherein one surfaces of the plurality of signal leads and the fixed potential lead, and the plurality of bonding pads formed over the main surface of the first semiconductor chip are respectively electrically connected to one another by the plurality of wires, the other surfaces of the plurality of signal leads and the fixed potential lead, and the plurality of bonding pads formed over the main surface of the second semiconductor chip are respectively electrically connected to one another by the plurality of wires, and the first and second semiconductor chips, the plurality of signal leads, the fixed potential leads, and the plurality of wires are sealed with a resin.
In the semiconductor device according to the present invention as well, suspension leads for respectively supporting the first and second semiconductor chips are fixedly secured to the main surface of either one of the first and second semiconductor chips.
Further, in the semiconductor device according to the present invention, the first and second semiconductor chips are placed in opposing relationship with being mutually shifted in positions so as to avoid the overlapping of parts of the backs thereof, one part of the fixed potential lead is fixedly secured to the non-overlapping area of the back of the first semiconductor chip, and the other part of the fixed potential lead is fixedly secured to the non-overlapping area of the back of the second semiconductor chip.
Furthermore, in the semiconductor device according to the present invention, parts of the fixed potential leads are interposed between the first and second semiconductor chips and fixedly secured to the backs thereof, and the other parts of the fixed potential leads extend outwardly from the sides of the first and second semiconductor chips.
REFERENCES:
patent: 5585665 (1996-12-01), Anjoh et al.
patent: 6087722 (2000-07-01), Lee et al.
patent: 6118184 (2000-09-01), Ishio et al.
patent: 6153922 (2000-11-01), Sugiyama et al.
patent: 6215192 (2001-04-01), Hirata et al.
patent: 6252299 (2001-06-01), Masuda et al.
patent: 6335227 (2002-01-01), Tsubosaki et al.
patent: 5-82719 (1993-04-01), None
patent: 7-58281 (1995-03-01), None
patent: 10-506226 (1998-06-01), None
Dang Phuc T.
Mattingly Stanger & Malur, P.C.
Nelms David
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