Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2001-03-08
2002-08-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S676000, C257S680000, C257S704000, C257S710000, C257S730000, C257S731000
Reexamination Certificate
active
06433412
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly to a technology effectively applied to a semiconductor device having a package mounted with a semiconductor chip and a passive element on the same substrate.
BACKGROUND OF THE INVENTION
Japanese Patent Laid-Open No. 46098/1996 (U.S. Pat. No. 5,533,256) discloses a package having a heat sink for radiating heat to the outside of a semiconductor chip formed with an integrated circuit (hereinafter, simply referred to as chip).
According to one mode of the package described in this publication, a chip is mounted by bonding it face down on a pad formed at an upper face of a module substrate via a solder ball. The pad and the solder ball are sealed by a seal member filled in a clearance between the module substrate and the chip.
One or more electronic devices such as a decoupling condenser is mounted along with the chip at the upper face of the module substrate. Further, a cap for sealing the chip and the electronic devices are fixedly attached to the upper face of the module substrate via the seal member and the heat sink is fixedly attached to an upper face of the cap via an adhering agent. A clearance between an upper face (rear face) of the chip and a lower face of the cap is filled with a heat conductive member and heat generated at the chi is transmitted to the heat sink via the heat conductive member and the cap.
According to other mode of the package described in the publication, the heat sink is directly bonded to the upper face (rear face) of the chip via a double-sided pressure-sensitive heat-conductive adhering tape. According to the mode, a cap for sealing the chip and the electronic devices is eliminated and accordingly, heat generated by the chip is transmitted to the heat sink more efficiently.
SUMMARY OF THE INVENTION
According to a high-speed LSI in recent years, reduction of noise in driving thereof poses an important problem and as a countermeasure against noise, a small-sized large capacity chip condenser is mounted on a substrate mounted with the chip to thereby reduce noise in a middle frequency area.
In this case, it is preferred that the condenser is arranged as close proximity as possible to the chip to thereby shorten wirings connecting both. However, a heat generating amount of the chip formed with the high-speed LSI is large and accordingly, when the condenser is arranged at an extremely close proximity of the chip, the condenser is exposed to an abrupt temperature change when operating the chip and a deterioration in connection reliability between the condenser and the substrate poses a problem.
Further, as in the package described in the publication, according to a package sealing the chip and the condenser mounted on the substrate by a cap, when a heat conductive member is filled between the chip and the cap in fabrication steps thereof, a large amount of the heat conductive member must be supplied with an object of absorbing dimensional tolerance of the cap and accordingly, when the condenser is arranged at the extreme proximity of the chip, the heat conductive member extruded from an end portion of the chip is brought into contact with the condenser.
As a result, the condenser is not only exposed to radiation heat from the chip but is exposed to intense heat conducted from the heat conductive member and the deterioration of the connection reliability in connecting to the substrate poses further serious problem. Further, when the heat conductive member comprises an electricity conductive material such as an Ag paste, there also poses a problem that the chip and the condenser or the condensers are short-circuited via the heat conductive member.
It is an object of the invention to provide a technology for promoting connection reliability of a passive element mounted at a vicinity of a chip.
It is other object of the invention to provide a technology to ensure electric reliability of a passive element mounted at a vicinity of a chip.
The object and other object and a novel feature of the invention will become apparent from description and attached drawings of the specification.
A simple explanation will be given of an outline of representative aspects of the invention disclosed in the application as follows.
According to an aspect of the invention, there is provided a semiconductor device comprising a substrate having a wiring layer, a semiconductor chip mounted onto a main face of the substrate in face down bonding, a passive element mounted onto the main face of the substrate, a seal resin filled between a main face of the semiconductor chip and the main face of the substrate, a cap for sealing the semiconductor chip and the passive element, and a heat conductive member filled between the cap and the semiconductor chip, wherein the passive element is arranged in an area coated with the seal resin and at least a portion thereof is covered by the seal resin.
According to other aspect of the invention, there is provided a method of manufacturing a semiconductor device comprising following steps:
(a) a step of mounting a semiconductor chip onto a main face of a substrate having a wiring layer in face down bonding;
(b) a step of mounting a passive element to a vicinity of an area mounted with the semiconductor chip on the main face of the substrate;
(c) a step of filling a seal resin into a clearance between a main face of the semiconductor chip and the main face of the substrate and covering the passive element by the seal resin;
(d) a step of supplying a heat conductive member on an upper face of the semiconductor chip; and
(e) a step of fixedly attaching a cap for sealing the semiconductor chip and the passive element onto an upper face of the semiconductor chip via a heat conductive member.
REFERENCES:
patent: 6165885 (2000-12-01), Gaynes et al.
patent: 6239486 (2001-05-01), Shimizu et al.
patent: 8-46098 (1996-02-01), None
Ando Hideko
Kikuchi Hiroshi
Sato Toshihiko
Shimizu Tomo
Yoshida Ikuo
Mattingly Stanger & Malur, P.C.
Nelms David
Tran Mai-Huong
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