Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-03-07
2002-07-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S676000, C257S777000
Reexamination Certificate
active
06420783
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, particularly relates to technique effective to apply to a semiconductor device that seals laminated two semiconductor chips in one resin sealing body.
For the high density mounting of semiconductor chips, a stacked semiconductor device in which two semiconductor chips are laminated and are sealed in one resin sealing body is developed. For this type of stacked semiconductor device, various structures are proposed and produced as a product. For example, in Japanese published unexamined patent publication No. Hei 9(1997)-153589 (Laid-Open date: Jun. 10, 1997), a stacked semiconductor device in which a die pad (also called a tub) is not provided and two semiconductor chips are bonded with the respective rear surfaces (surfaces respectively opposite to a circuit forming surface) opposite is disclosed.
SUMMARY OF THE INVENTION
The inventors of the invention found the following problems as a result of discussing the stacked semiconductor device.
(1) A semiconductor chip is mainly provided with a semiconductor substrate, a multilayer wiring layer formed by laminating plural sets of an insulating layer and a wiring layer on the circuit forming surface of the semiconductor substrate and a surface passivation film (a final passivation film) formed so that the surface passivation film covers the multilayer wiring layer. For a semiconductor substrate, a silicon substrate for example is used, for an insulating layer, a silicon oxide film for example is used, for a wiring layer, a metallic film such as an aluminum film, an aluminum alloy film, a copper film and a copper alloy film is used and for a surface passivation film, polyimide resin high in an adhesive property to the resin of a resin sealing body for example is used. That is, as the circuit forming surface and the rear surface mutually opposite of the semiconductor chip are different in a coefficient of thermal expansion, the semiconductor chip is generally warped in a direction in which the rear surface is convex.
In the meantime, the rear surfaces of two semiconductor chips are generally bonded by applying an adhesive to the rear surface of one semiconductor chip and afterward, pressing the other semiconductor chip against the rear surface of one semiconductor chip with the rear surface of the other semiconductor chip opposite to the rear surface of one semiconductor chip. At this time, as shown in FIG.
29
(
a
), as two semiconductor chips
101
are warped in a direction in which the respective rear surfaces are convex, the failure of wetting of an adhesive
102
often occurs in a periphery between the two semiconductor chips
101
and clearance
103
is formed in the periphery between the two semiconductor chips
101
. As an interval of this clearance
103
is slight, resin
104
does not fully get into the clearance
103
and a void
105
is formed between the two semiconductor chips
101
as shown in FIG.
29
(
b
) when a resin sealing body is formed according to a transfer molding method. Particularly, as multiple fillers (for example, silica) are generally mixed in the resin
104
to reduce stress, the resin
104
is prevented from getting into the clearance
103
narrower than the particle diameter of the filler by the filler and the void
105
is easily formed.
As a problem that thermal stress concentrates on the void
105
and the semiconductor chip
101
cracks with the void
105
in the center, in a curing process (a hardening process) after a resin sealing body is formed occurs in case such a void
105
is formed between the two semiconductor chips
101
, the yield of the stacked semiconductor device is deteriorated.
FIGS.
29
(
a
) and
29
(
b
) are typical sectional views for explaining the problem of a conventional type, a reference number
106
denotes a die and
107
denotes a cavity.
(2) The thinning of a stacked semiconductor device is demanded. As the two semiconductor chips are laminated with the respective rear surfaces opposite in the case of the stacked semiconductor device, the thickness of the resin of a resin sealing body on the circuit forming surface of one semiconductor chip is required to be increased by quantity equivalent to the height of a loop of wire (the height from the circuit forming surface of the semiconductor chip to the vertex in a vertical direction) electrically connecting an electrode formed on the circuit forming surface of one semiconductor chip and a lead, and the thickness of the resin of a resin sealing body on the circuit forming surface of the other semiconductor chip is required to be increased by quantity equivalent to the height of a loop of wire electrically connecting an electrode formed on the circuit forming surface of the other semiconductor chip and a lead. That is, as the thickness of the resin of each resin sealing body on the respective circuit forming surfaces of the two semiconductor chips is required to be increased in case the two semiconductor chips are laminated with their respective rear surfaces opposite, it is difficult to thin the semiconductor device.
The object of the invention is to provide technique for enabling the enhancement of the yield of a semiconductor device in which plural semiconductor chips are laminated and are sealed in one resin sealing body.
Another object of the invention is to provide technique for enabling the thinning of a semiconductor device in which plural semiconductor chips are laminated and are sealed in one resin sealing body.
The object and another object of the invention and a new characteristic will be clarified by the description of the specification and the attached drawings.
The brief outline of the representative of the invention disclosed in this application is as follows.
(1) A semiconductor device according to the invention is based upon a semiconductor device provided with a first semiconductor chip and a second semiconductor chip respectively in a square laminated with their respective one main surfaces opposite to each other, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead, and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and the part of the supporting lead is formed so that it is narrower than the respective sides of the first semiconductor chip and the second semiconductor chip.
(2) A semiconductor device according to the invention is based upon a semiconductor device provided with a first semiconductor chip which has opposite first main surface and second main surface, the plane of which is formed in a square and which is provided with plural electrodes arranged along a first side on the side of the first side of opposite first side and second side of the first main surface, a second semiconductor chip which has opposite first main surface and second main surface, the plane of which is formed in a square and which is provided with plural electrodes arranged along a first side on the side of the first side of opposite first side and second side of the first main surface, plural first leads each of which has an inner part and an outer part, the inner parts of which are arranged outside the first side of the first semiconductor chip and the inner parts of which are respectively electrically connected to the electrodes of the first semiconductor chip via each conductive wire, plural second leads each of which has an inner part and an outer part, the inner parts of which are arranged outside the first side of the second semiconductor chip and the inner parts of which are respectively electrically connected to the electrodes of the second semiconductor chip via each conductive wire and a resin sealing body that seals the first semiconductor chip, the second semicondu
Fujioka Shunichiro
Ide Takuji
Niihara Eiji
Ueno Mitsue
Wada Takashi
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tran Mai-Huong
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