Semiconductor device and a method of manufacturing the same

Details Semiconductor device and a method of manufacturing the same Semiconductor device and a method of manufacturing the same

2011-08-30

2011-08-30

Wagner, Jenny L. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE21237

Reexamination Certificate

active

08008788

ABSTRACT:
A technique for positioning a semiconductor chip and a mounting substrate with high precision using an alignment mark. In a semiconductor chip, a mark is formed in an alignment mark formation region over a semiconductor substrate in the same layer as an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. Pattern P1ais formed in the same layer as a second layer wiring, pattern P1bis formed in the same layer as a first layer wiring, pattern P2is formed in the same layer as a gate electrode, and pattern P3is formed in the same layer as an element isolation region.

REFERENCES:
patent: 5640049 (1997-06-01), Rostoker et al.
patent: 6242792 (2001-06-01), Miura et al.
patent: 7534695 (2009-05-01), Suzuki et al.
patent: 7825529 (2010-11-01), Horii
patent: 2005/0161836 (2005-07-01), Yudasaka et al.
patent: 11-330247 (1990-11-01), None
patent: 2000-182914 (2000-06-01), None

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