Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-07-29
2001-06-05
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S510000, C257S521000
Reexamination Certificate
active
06242788
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation region by a trench element isolation structure out of methods of defining the element formation region in a semiconductor substrate, and a method of manufacturing the same.
2. Description of the Prior Art
A known example of structures for electrically isolating elements on a semiconductor substrate is a trench element isolation structure. In this element isolation structure, an insulating film made of, for example, an oxide film is buried in a trench formed in, for example, a silicon semiconductor substrate to define an element active region.
In this trench element isolation structure, an electric field tends to concentrate at the end of an element isolation region, resulting in a low threshold voltage of the MOS transistor.
To solve this problem, Japanese Patent Laid-Open Nos. 63-305527 and 1-107554 have disclosed structures in which concentration of electric fields at the end of the element isolation region is relaxed by tapering the upper portion of the trench side wall and vertically forming its lower portion in a trench element isolation structure.
Japanese Patent Laid-Open No. 6-177239 has disclosed a structure in which the entire side wall of a trench is tapered from the top to the bottom in a trench element isolation structure.
Japanese Patent Laid-Open No. 7-161808 has disclosed a method of increasing the angle of the side wall of a trench at its upper end by wet etching.
In the method disclosed in Japanese Patent Laid-Open No. 63-305527, an insulating film is buried in a trench formed in a semiconductor substrate so as not to reach the surface of the semiconductor substrate, and then the edge defined by the trench side wall and semiconductor substrate surface is anisotropically etched away to taper the upper end of the trench side wall.
In the method disclosed in Japanese Patent Laid-Open No. 1-107554, an oxide film is formed on a semiconductor substrate and processed into a mask shape used to form a trench, and then isotropic plasma etching is performed before forming a trench. The upper end of the side wall of a prospective trench is tapered in advance, and anisotropic etching is performed to form a trench, thereby completing a trench having a tapered upper end.
In the method disclosed in Japanese Patent Laid-Open No. 6-177239, dry etching is performed using a cap oxide film as a mask with nitrogen gas and oxygen gas to form a trench having an entirely tapered side wall.
In the method disclosed in Japanese Patent Laid-Open No. 63-305527, however, since the etching process window is narrow, and the edge defined by the trench side wall and semiconductor substrate surface is rounded by wet etching, a tapered surface formed from a uniform inclined surface is difficult to form.
In the method disclosed in Japanese Patent Laid-Open No. 1-107554, since the upper end is tapered by isotropic plasma etching, no inclined surface can be formed. Further, the trench is directly deepened by anisotropic etching after tapering, so the tapered shape may change upon this anisotropic etching.
In the methods disclosed in Japanese Patent Laid-Open Nos. 63-305527 and 1-107554, an oxide film must be directly formed on the semiconductor substrate to fill the trench after tapering, and etched back while being left in the trench. However, no stopper film effective for etch-back is formed.
The oxide film filling the trench, therefore, becomes flush with the semiconductor substrate surface upon etch-back. When a gate wiring layer or interconnect for a MOS transistor is formed on the oxide film filling the trench, the distance between the gate wiring layer and the semiconductor substrate is short. Accordingly, even if the upper portion of the trench is tapered, an electric field concentrates at this portion.
In the method disclosed in Japanese Patent Laid-Open No. 7-161808, since the upper end of the trench is shaped into an inclined surface by wet etching, the trench width unnecessarily widens, resulting in a large element isolation area. This obstructs micropatterning of semiconductor devices and damages the semiconductor substrate exposed in the trench.
As described above, since the taper angle of the trench upper end cannot be uniformly controlled, and the element isolation region is even with the semiconductor substrate surface, concentration of an electric field at the end of the element isolation region cannot be effectively relaxed.
When, therefore, a MOS transistor is formed using the trench element isolation structure in the prior art, the threshold voltage undesirably varies and decreases.
In the method disclosed in Japanese Patent Laid-Open No. 6-177239, since the entire side wall of the trench is tapered, no trench except for a trench having a constant aspect ratio can be formed. In other words, the trench depth is naturally determined by the trench width. To ensure satisfactory element isolation performance, the element isolation region must be made wide, which obstructs micropatterning of elements.
In addition, in the trench element isolation structure, when a multilayered film serving as a trench formation mask is removed or when cleaning is performed later, the end of the insulating film filling the trench is removed to recess it from semiconductor substrate surface.
If the gate electrode of a MOS transistor is formed over the recess, an electric field concentrates at the boundary between the insulating film and the semiconductor substrate, i.e., the element isolation end of the trench element isolation structure, resulting in a low threshold voltage and a large leakage current of the transistor.
Methods for solving this problem are disclosed in Japanese Patent Laid-Open Nos. 6-21210 and 7-273180.
According to these references, a multilayered film serving as a trench formation mask is formed on a semiconductor substrate, a trench formation portion is selectively removed to form an opening, and then a silicon oxide film is formed by CVD on the entire surface of the semiconductor substrate to temporarily fill the opening.
The silicon oxide film is removed from the multilayered film by anisotropic etching to form a side wall made of the silicon oxide film on the side wall of the multilayered film in the opening. In forming a trench in the semiconductor substrate, etching is performed using the side wall and the multilayered film as a mask.
After forming the trench, a silicon oxide film is formed by CVD to fill the trench, the silicon oxide film is removed from the multilayered film, and then the multilayered film used as a mask is removed to complete the trench element isolation structure.
According to these methods, since the opening is narrowed by the side wall on the multilayered structure, the side wall made of the silicon oxide film is left at the side edge of the silicon oxide film buried in the trench upon removing the multilayered film. Therefore, the trench element isolation structure is wider than the trench width by the side wall thickness in the semiconductor substrate.
In removing the multilayered film or in subsequent cleaning, the side wall is removed before the silicon oxide film filling the trench is removed. Accordingly, the side wall serves as a protective film to prevent formation of the above-described recess at the element isolation end.
However, even if the side wall is formed of the silicon oxide film to widen the trench element isolation structure, as described above, the silicon oxide film forming the side wall does not satisfactorily function as a protective film against etching or cleaning.
More specifically, in the above methods, the silicon oxide film formed by CVD is used as a side wall. Hot phosphoric acid is employed in order to remove a silicon nitride film generally used as a trench formation mask film, but the silicon oxide film formed by CVD cannot attain a sufficiently high etching selectivity with respect to the silicon nitride film.
Similarly, the side wall made of the silicon oxide film cannot sufficientl
Connolly Bove Lodge & Hutz
Crane Sara
Nippon Steel Corporation
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