Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2010-04-30
2011-12-27
Lee, Cheung (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S128000, C438S257000, C438S599000, C257SE21179, C257SE21422, C257SE21680
Reexamination Certificate
active
08084303
ABSTRACT:
In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an first insulating film formed thereon. Further, over the entire main surface of the semiconductor substrate, an second insulating film is deposited so that it covers the pattern of the first insulating film and a gate electrode. The second insulating film is formed by a silicon nitride film formed by a plasma CVD method. The first insulating film is formed by a silicon nitride film formed by a low-pressure CVD method. By the provision of such an first insulating film, it is possible to suppress or prevent water or hydrogen ions from diffusing to the floating gate electrode, and therefore, the data retention characteristics of a flash memory can be improved.
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Shiba Kazuyoshi
Yashima Hideyuki
Lee Cheung
Miles & Stockbridge P.C.
Renesas Electronics Corporation
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