Semiconductor device and a method of manufacturing the same

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout

Reexamination Certificate

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C438S128000, C438S257000, C438S599000, C257SE21179, C257SE21422, C257SE21680

Reexamination Certificate

active

07732261

ABSTRACT:
In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of a first insulating film formed thereon. Further, over the entire main surface of the semiconductor substrate, a second insulating film is deposited so that it covers the pattern of the first insulating film and a gate electrode. The second insulating film is formed by a silicon nitride film formed by a plasma CVD method. The first insulating film is formed by a silicon nitride film formed by a low-pressure CVD method. By the provision of such a first insulating film, it is possible to suppress or prevent water or hydrogen ions from diffusing to the floating gate electrode, and therefore, the data retention characteristics of a flash memory can be improved.

REFERENCES:
patent: 7601581 (2009-10-01), Taniguchi et al.
patent: 2007/0058441 (2007-03-01), Oka et al.
patent: 2007/0210388 (2007-09-01), Shiba
patent: 2009/0093096 (2009-04-01), Shiba
patent: 2002-16249 (2002-01-01), None
patent: 2007-110073 (2007-04-01), None
patent: WO 2005/101519 (2005-10-01), None

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