Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2009-07-15
2010-06-29
Smith, Bradley K (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S390000
Reexamination Certificate
active
07745903
ABSTRACT:
A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an isolation width of smaller than 0.3 μm, a planar shape of each active region ACT is made polygonal by cutting off the corners of a quadrangle, thereby suppressing the occurrence of a crystal defect in the active region ACT and diminishing a leakage current flowing between the source and drain of a field effect transistor. In a sense amplifier data latch section which is required to have a layout of a small margin in the alignment between a gate G of a field effect transistor and the active region ACT, the field effect transistor is disposed at a narrow pitch by making the active region ACT quadrangular.
REFERENCES:
patent: 2009/0001502 (2009-01-01), Tilke et al.
patent: 2009/0090992 (2009-04-01), Lerner et al.
patent: 2001-15586 (2001-01-01), None
Adachi Tetsuo
Sato Akihiko
Antonelli Terry Stout & Kraus LLP
Renesas Electronics Corp.
Smith Bradley K
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