Semiconductor device and a manufacturing method thereof

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185050, C365S230030

Reexamination Certificate

active

08036036

ABSTRACT:
A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the plurality of cell gates being located between one pair of the first and second selection gates within a corresponding block of the memory cell block.

REFERENCES:
patent: 7084440 (2006-08-01), Sel et al.
patent: 7112858 (2006-09-01), Inaba et al.
patent: 7723807 (2010-05-01), Nishiyama
patent: 2006/0046422 (2006-03-01), Tran et al.
patent: 2007/0141780 (2007-06-01), Higashitani
patent: 7-263677 (1995-10-01), None
patent: 2002-280388 (2002-09-01), None
patent: 2004-15056 (2004-01-01), None
patent: 2006-156657 (2006-06-01), None

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