Static information storage and retrieval – Floating gate – Disturbance control
Reexamination Certificate
2002-03-01
2004-03-30
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Disturbance control
C365S185170, C365S185280
Reexamination Certificate
active
06714447
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the techniques of semiconductor devices and integrated circuit cards. More particularly, the present invention relates to the techniques employable effectively for semiconductor devices and integrated circuit cards provided with flash memories (EEPROM: Electric Erasable Programmable Read Only Memory) respectively.
BACKGROUND OF THE INVENTION
The flash memory (EEPROM) examined by the present inventor et al employs a method that sets the potential of a data line connected to a selected memory cell to a ground potential, then applies a positive high voltage (write voltage) to the word line (the control gate electrode of the selected memory cell) connected to the selected memory cell, thereby generating an FN (Fowler-Nordheim) tunneling phenomenon so as to inject electrons in the floating gate electrode of the selected memory cell.
According to the method, however, because the control gate electrodes of other non-selected memory cells are also connected electrically to the word line to which the control gate electrode of the selected memory cell is connected electrically, the write voltage is applied to the control gate electrodes of the non-selected memory cells. As a result, a write errors occur sometimes in those non-selected memory cells. To prevent such write errors, therefore, writing of data in those non-selected memory cells must be disabled.
SUMMARY OF THE INVENTION
This write disable operation is executed as follows, for example. Prior to the application of the write voltage to a selected word line so as to write data in a selected memory cell, a writing disable voltage of about 6V is applied to the drains (that is, the data line) of the non-selected memory cells, thereby charging the writing disable voltage to the selected sub-source line. The channel potential of each non-selected memory cell then rises up to the potential of the writing disable voltage when the writing disable voltage is applied to the word line for the data writing. The gate electric field of each non-selected memory cell is thus eased and injection of electrons in the floating gate electrode thereof can be suppressed.
Such a flash memory is disclosed by, for example, U.S. Pat. No. 6,046,936 corresponding to the official gazette of Japanese Patent Application Laid-Open No. Hei 11 (1999)-232886 or Japanese Patent Application Laid-Open No. Hei 10 (1998)-275484. The flash memory (EEPROM) is an AND one that makes good use of the tunneling phenomenon for writing/erasing data therein/therefrom.
The present inventor et al have found for the first time that hot electrons are generated in non-selected memory cells in such a write disable operation, since a transient channel current used to charge the selected sub-source line flows in each non-selected memory cell for a moment while a positive voltage is applied to both control electrode and drain thereof. When such hot electrons are affected by the gate electric field, thereby being injected in the floating gate of a non-selected memory cell, the threshold voltage of the non-selected memory cell rises, causing wrong writing, that is, a so-called write disturbance phenomenon. In other words, data is written in the non-selected memory cell due to a mechanism completely different from the tunneling phenomenon.
Especially, when memory cells are reduced in size for higher integration, the electric field at the end of the drain of each of those memory cells becomes stronger. This makes it easier to generate such hot electrons. As a result, the write disturbance phenomenon as described above comes to occur more frequently. For a flash memory (EEPROM) in which writing and erasing of data can be repeated, a problem arises due to such repetitive operations while no problem arises from occurrence of one or a few times of write disturbance.
Under such circumstances, it is an object of the present invention to provide a technique that can suppress or prevent such a write disturbance phenomenon from occurring in each write-disabled non-selected memory cell in a semiconductor device provided with a plurality of non-volatile memory cells, in each selected one of which data can be written electrically through the tunneling phenomenon.
Those and other objects, as well as new features of the present invention will become more apparent from the description of this specification and the accompanying drawings.
Hereinafter, the representative items of the present invention disclosed in this specification will be described briefly.
Concretely, the semiconductor device of the present invention provided with a plurality of non-volatile memory cells, in each selected one of which data can be written electrically through the tunneling phenomenon is structured so as to generate a punch-through phenomenon between the source and the drain of each non-selected memory cell when a writing disable voltage is applied to the drain thereof.
REFERENCES:
patent: 4542485 (1985-09-01), Iwahashi et al.
patent: 4897815 (1990-01-01), Tanaka et al.
patent: 6046936 (2000-04-01), Tsujikawa et al.
patent: 10-275484 (1998-10-01), None
Patent Abstracts of Japan 10275484 Oct. 13, 1998.
Satoh Akihiko
Takahashi Masahito
Antonelli Terry Stout & Kraus LLP
Le Vu A.
Renesas Technology Corporation
LandOfFree
Semiconductor device and a integrated circuit card does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and a integrated circuit card, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and a integrated circuit card will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3254838