Semiconductor device analyzer, method for...

Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C703S014000, C716S030000, C700S121000

Reexamination Certificate

active

07016820

ABSTRACT:
A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator “s”. The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.

REFERENCES:
patent: 5469366 (1995-11-01), Yang et al.
patent: 5986263 (1999-11-01), Hiroi et al.
patent: 6031986 (2000-02-01), Milsom
patent: 6360190 (2002-03-01), Kumashiro
patent: 10-261004 (1998-09-01), None
Deng et al., W.K. Elements Extraction og GaAs Dual-Gate MESFET Small-Signal Equivalent Circuit, IEEE Transactions on Microwave Theory and Techniques, vol. 46, No. 12, Dec. 1998, pp. 2383-2390.
Kevin J. Kerns, et al., “Stable and Efficient Reduction of Substrate Model Networks Using Congruence Transforms,” IEEE/ACM International Conference on Computer Aided Design Digest of Technical Papers, 1995, pp. 207-214.
Eli Chirpout, et al., “Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis,” Kluwer Academic Publishers, Chapters 1,2 and 4, 1994, pp. 1-38, 67-84.
Balsha R. Stanisic, et al., “Addressing Substrate Coupling in Mixed-Mode IC's: Simulation and Power Distribution Synthesis,” IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 226-238.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device analyzer, method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device analyzer, method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device analyzer, method for... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3586516

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.