Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2000-02-14
2002-08-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Powering
Conservation of power
C365S226000, C365S189070, C365S189090, C365S189110, C365S201000
Reexamination Certificate
active
06434078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device having a circuit associated with a reliability evaluation testing.
2. Description of the Background Art
Recently, together with the advancement of the integration of semiconductor devices and the miniaturization of MOS transistors, a thickness of a gate oxide film of an MOS transistor have been decreasing, leading to the decreased breakdown voltage of the gate oxide film. Therefore a high gate voltage may have an adverse effect on the reliability of an MOS transistor.
In some systems using a semiconductor memory device, a voltage required for an operation of the semiconductor memory device is lower than a power supply voltage of the system itself. In such a case, the power supply voltage for the semiconductor memory device is generally supplied from the power supply voltage of the system itself, by generating an internal power supply voltage required for the operation of the semiconductor memory device by pulling down the voltage inside the semiconductor memory device.
A circuit generating the internal power supply voltage in this manner is called a voltage down converter. Use of such a voltage down converter allows the substantial reduction of the power consumption by the semiconductor memory device thus stabilizing the internal power supply voltage used therein.
Now, the reliability evaluation test will be described.
Generally, a life of a device can be divided into three periods based on the characteristics of failures. That is, an early failure period, followed by a random failure period and a wear-out failure period.
Immediately after the device is put under use, the early failure period starts. During this period, early failures originating from defects at the time of manufacture of the device are revealed. The rate of an early failure rapidly decreases with time.
Then a long random failure period with a low failure rate lasts for a certain period.
As the device approaches the end of its useful life, it enters the wear-out failure period where the failure rate dramatically increases.
The device is desirably used in the random failure period, which is regarded as equivalent to the service life of the device. Therefore, the random failure period is required to last long with a low and constant failure rate, in order to enhance the device reliability.
On the other hand, a screening is indispensable for precluding early failures, in which devices are subjected to accelerated aging for a prescribed time period, whereby defective devices are screened out. A screen testing which ensures that the early failure rate rapidly decreases against time to enable immediate commencement of the random failure period is desirable in order to perform the screening effectively in a short time period.
Currently a high temperature operation test (burn-in test) is generally performed as a screening procedure. The burn-in test allows a direct evaluation of a dielectric film using an actual device. During the burn-in test, every defective factor including a migration of an aluminum interconnection is revealed by applying a high temperature and high-field stresses.
When the device is operated under a high temperature to enhance acceleration, the burn-in test becomes particularly effective.
FIG. 15
is a block diagram showing a configuration of a voltage down converter portion of a conventional semiconductor device adaptable for the burn-in test.
Referring to
FIG. 15
, the voltage down converter of the conventional semiconductor device includes: a capacitor
212
arranged between an external power supply potential Ext.Vcc and a ground potential; a capacitor
220
arranged between an internal power supply potential Int.Vcc and the ground potential; a reference voltage generation circuit
216
generating a reference potential for internal power supply potential Int.Vcc at a normal operation; a differential amplifier
218
powered by external power supply potential Ext.Vcc and setting an internal power supply potential Int.Vcc of the same level as an output voltage of reference voltage generation circuit
216
; and a P channel transistor
214
having a gate receiving a burn-in mode detection signal /STR, a source coupled to external power supply potential Ext.Vcc and a drain coupled to internal power supply potential Int.Vcc.
In a normal mode other than a test mode for the reliability evaluation, burn-in mode detection signal /STR is at a logical high (H) level and P channel transistor
214
is off.
In the test mode for the reliability evaluation, burn-in mode detection signal /STR attains a logical low (L) level and a node supplied with internal power supply potential Int.Vcc and a node supplied with external power supply potential Ext.Vcc are connected together via P channel transistor
214
, thus internal power supply potential Int.Vcc is rendered equal to external power supply potential Ext.Vcc.
In such a voltage down converter as the one shown in
FIG. 15
, however, transistor
214
, which short-circuits a node receiving external power supply potential Ext.Vcc and a node receiving internal power supply potential Int.Vcc at the time of testing, must be large enough to secure the current driving capability. Such a large transistor required for the testing of semiconductor devices causes a chip area to increase.
A method for rendering internal power supply potential Int.Vcc the same level as external power supply potential Ext.Vcc using an output driving transistor included in a differential amplifier portion is disclosed in Japanese Patent Laying-Open No. 6-103793.
FIG. 16
is a circuit diagram showing a configuration of a voltage down converter disclosed in the aforementioned Japanese Patent Laying-Open No. 6-103793.
The voltage down converter shown in
FIG. 16
includes: a reference voltage generation circuit
2100
for generating a reference voltage Vref; a comparator
2200
for receiving and comparing internal power supply voltage Int.Vcc and reference voltage Vref; a driver P
5
controlled by comparator
2200
and pulling down external power supply voltage Ext.Vcc to the level of internal power supply voltage Int.Vcc; a burn-in reference voltage generation circuit
2300
; series-connected inverters Il and I
2
receiving an output of node G
3
of burn-in reference voltage generation circuit
2300
as an input; an inverter I
3
receiving an output of inverter I
2
; an N channel transistor N
4
having a gate receiving an output of inverter I
3
and connecting an output node G
1
of comparator
2200
and a node G
2
connected to a gate of driver P
5
; a P channel transistor P
3
having a gate receiving the output of inverter I
2
and connecting node G
1
and node G
2
; and an N channel transistor N
5
having a gate receiving the output of inverter I
2
and coupling node G
2
with a ground potential Vss.
Comparator
2200
includes an N channel transistor N
3
having a gate receiving reference voltage Vref and a source coupled to ground potential Vss, an N channel transistor N
1
having a gate receiving reference voltage Vref and connecting a drain of N channel transistor N
3
and node G
1
, an N channel transistor N
2
having a gate receiving internal power supply potential Int.Vcc and a source connected to the drain of N channel transistor N
3
, a P channel transistor P
2
having a gate receiving a drain potential of N channel transistor N
2
and coupling the drain of N channel transistor N
2
and external power supply potential Ext.Vcc and a P channel transistor P
1
having a gate receiving a potential from the drain of N channel transistor N
2
and coupling node G
1
and external power supply potential Ext.Vcc.
FIG. 17
is a waveform diagram illustrating an operation of the voltage down converter shown in FIG.
16
.
Referring to
FIGS. 16 and 17
, the voltage down converter operates normally during the time period t
1
-t
2
.
Internal power supply potential Int.Vcc is applied to each circuit block such as a memory element in a
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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