Semiconductor device allowing accurate characteristics test

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365233, 365193, 365201, G11C 800

Patent

active

054002907

ABSTRACT:
In response to an external control signal, a first timing detecting circuit and a high voltage detecting circuit detect setting of a signature mode and provide a signature mode signal to a second timing detecting circuit. The second timing detecting circuit outputs an output buffer activating signal to the output buffer in response to the external control signal. In response to the output buffer activating signal, the output buffer detects an internal supply voltage and provides the same to an external pin.

REFERENCES:
patent: 5046052 (1991-09-01), Miyaji et al.
"16M DRAM" Nikkei Micro Devices, Oct. 1991 pp. 48-52.
"Application of a High-Voltage Pumped Supply for Low-Power DRAM", R. C. Foss et al., 1992, Symposium on FLSI Circuits Digest of Technical Papers pp. 106-107.
"A 34-ns 16-Mb DRAM with Controllable Voltage Down-Converter", Hidaka et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988 pp. 1020-1026.
"Dual-Operating-Voltage Scheme for a Single 5-V 16-Mbit DRAM", Horiguchi et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988 pp. 1128-1132.

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