Semiconductor device adapted to minimize clock skew

Details Semiconductor device adapted to minimize clock skew Semiconductor device adapted to minimize clock skew

2007-06-26

2007-06-26

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000

Reexamination Certificate

active

10990537

ABSTRACT:
A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

REFERENCES:
patent: 6049239 (2000-04-01), Eto et al.
patent: 6323714 (2001-11-01), Naffziger et al.
patent: 6342796 (2002-01-01), Jung
patent: 6356158 (2002-03-01), Lesea
patent: 6452432 (2002-09-01), Kim
patent: 6765976 (2004-07-01), Oh
patent: 2001-274341 (2001-10-01), None
U.S. Appl. No. 10/990,537, Nov. 18, 2004, Shiratake et al.
U.S. Appl. No. 11/342,617, Jan. 31, 2006, Fujita et al.

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