Semiconductor device

Details Semiconductor device Semiconductor device

2000-12-06

2002-04-16

Jackson, Stephen W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S058000, C361S091100, C361S111000

Reexamination Certificate

active

06373668

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising an MOS transistor formed on an SOI (silicon(semiconductor)-on-insulator) substrate and, in particular, to its I/O protection function.
2. Description of the Background Art
In MOS transistors formed on SOI substrates in which a silicon thin film is formed on an insulating substrate (referred to as “SOI device” in some cases), its source and drain regions reach the insulating substrate so that each junction capacity is reduced, permitting high speed and low dissipation power operation.
Specifically, in MOS transistors formed on normal bulk silicon substrates (referring to as “substrate device” in some cases), the respective junction capacity of drain and source regions is increased at low voltages and its performance (particularly, operation speed) is extremely lowered. On the other hand, since SOI devices have less components for the respective junction capacity of drain and source regions, so that they have little performance degradation, permitting high speed and low dissipation power operation.
As described, since SOI devices provide high speed and low dissipation power operation, they are highly anticipated to be utilized as devices for portable apparatuses.
Although SOI devices are expected to be used as devices for low-voltage operation, they have poor ESD (Electro Static Discharge) resistance in I/O protection circuits. The reason for being called I/O protection circuit is that a surge voltage can be applied from output terminals as well as input terminals.
FIG. 23
is a sectional view of an SOI structure. As shown in the figure, a buried oxide film
2
is formed on a semiconductor substrate
1
, and an SOI layer
3
is formed on the oxide film
2
. The structure comprising the semiconductor substrate
1
, the buried oxide film
2
, and the SOI layer
3
, is called SOI substrate. A gate oxide film
4
is selectively formed on the SOI layer
3
, and a gate electrode
5
is formed on the gate oxide film
4
. The SOI layer
3
underlying the gate oxide film
4
serves as a channel region
8
, and regions of the SOI layer
3
adjacent to the channel region
8
serve as a drain region
6
and a source region
7
.
In the above SOI structure, heat generated when applied a surge voltage is accumulated by the presence of the buried oxide film
2
whose thermal conductivity is poor (about one-tenth of that of silicon). It is therefore liable to cause a thermal runaway or 2nd breakdown, resulting in permanent breakage of semiconductor devices on SOI substrates.
FIG. 24
is a graph diagram showing a process of a thermal runaway. This figure shows a process of a thermal runaway at the time of reverse bias connection, e.g., when an input voltage (surge voltage SV) is applied to a drain of an NMOS transistor Q
1
whose source and gate are grounded as shown in FIG.
25
. The thermal runaway process of
FIG. 24
comprises subprocesses P
1
to P
5
.
When a surge voltage SV far beyond ordinary ones is applied to the drain of the NMOS transistor Q
1
in
FIG. 25
, its drain voltage rises rapidly (P
1
) and reaches a breakdown induced voltage. Then, the transistor Q
1
causes an avalanche breakdown so that the current begins to flow, lowering to a holding voltage temporarily (P
2
). Thereafter, it starts to rise again (P
3
) and, when it reaches a thermal breakdown voltage, portions of the transistor Q
1
become a melted state so that the resistance value between the source and drain is rapidly lowered, causing a rapid voltage drop (P
4
). The flow of current concentrates on the transistor Q
1
that has caused such a rapid drop of resistance value between the source and drain, that is, a positive feedback is effected (P
5
). As a result, the transistor Q
1
is completely broken. For instance, as shown in
FIG. 26
, a large defect
10
due to the thermal breakdown occurs in the gate electrode
5
, thereby making the transistor operation impossible.
Generally, in cases where, as an I/O protection circuit on an SOI substrate, NMOS transistors are provided by a reverse bias, NMOS transistors having a channel width W are connected in parallel between an input (voltage) IN and a ground level as shown in FIG.
27
. In the case of
FIG. 27
, six NMOS transistors T
1
to T
6
whose gate is grounded are provided in parallel between an input IN and a ground level as shown in FIG.
28
. The NMOS transistor T
1
comprises a gate electrode
51
, a drain region
61
, and a source region
71
. The NMOS transistor T
2
comprises a gate electrode
52
, a drain region
61
, and a source region
72
. The NMOS transistor T
3
comprises a gate electrode
53
, a drain region
62
, and a source region
72
. The NMOS transistor T
4
comprises a gate electrode
54
, a drain region
62
, and a source region
73
. The NMOS transistor T
5
comprises a gate electrode
55
, a drain region
63
, and a source region
73
. The NMOS transistor T
6
comprises a gate electrode
56
, a drain region
63
, and a source region
74
. The input voltage IN as a surge voltage is input from an external input terminal or an external output terminal.
Providing the six NMOS transistors T
1
to T
6
in parallel between the input IN and the ground level as an I/O protection circuit on an SOI substrate, enables to distribute the current into the transistors T
1
to T
6
when the current flows between the input IN and the ground level.
If, however, one of the NMOS transistors T
1
to T
6
causes an avalanche breakdown and reaches a thermal breakdown voltage, a resistance value between the source and drain of such a transistor is rapidly lowered. As shown in a subprocess P
5
in
FIG. 24
, the flow of current concentrates on such a transistor that has reached a thermal breakdown voltage, failing to suppress this transistor from being broken.
Thus, with the I/O protection circuit utilizing the NMOS transistors of the conventional SOI structure, even if, in order to improve a surge resistance, a plurality of NMOS transistors in parallel connection constitute an I/O protection circuit as shown in
FIG. 27
, expected improvement in ESD resistance cannot be accomplished.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device formed on an SOI substrate has an I/O protection circuit portion including at least one first MOS transistor connected to an external terminal by a forward bias, and a plurality of second MOS transistors connected in parallel to the external terminal by a reverse bias. In this semiconductor device, a resistance value of each drain resistance of the plurality of second MOS transistors is set so that an ESD (Electro Static Discharge ) resistance of the plurality of second MOS transistors is approximately equal to or greater than that of the at least one first MOS transistor.
According to a second aspect of the invention, the semiconductor device of the first aspect further comprises an internal circuit portion that performs signal processing based on signals from the external terminal. In this semiconductor device, the internal circuit includes an MOS transistor for internal circuit having a conductivity type identical with that of the plurality of second MOS transistors, and the MOS transistor for internal circuit has a drain resistance whose resistance value is smaller than that of each drain resistance of the plurality of second MOS transistors.
According to a third aspect of the invention, in the semiconductor device of the second aspect, a plurality of first silicide layers are respectively provided on drain regions of the plurality of second MOS transistors, a second silicide layer is provided on a drain region of the MOS transistor for internal circuit, and the first silicide layer is thinner in thickness than the second silicide layer.
According to a fourth aspect of the invention, in the semiconductor device of the first aspect, the conductivity type of the at least one first MOS transistor and the-plurality of second MOS transistors is n-type.
According t

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