Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-04-17
2002-05-14
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S335000, C438S197000
Reexamination Certificate
active
06388280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated gate semiconductor device represented by a MOSFET, an IGBT and the like, and more particularly to an improvement of a reverse bias characteristic thereof.
2. Description of the Background Art
In recent years, attention has been given to a MOSFET or an IGBT as a switching element to be used for inverter control or the like.
FIG. 8
is a plan view showing a typical MOSFET. The MOSFET is a so-called vertical type MOSFET in which a gate wire bonding pad
2
and a source wire bonding pad
3
are provided on an upper main surface of a semiconductor substrate
1
. A large number of unit cells are arranged along a main surface of the semiconductor substrate
1
. Each of the unit cells functions as a single MOSFET. A region
40
where the unit cells are to be arranged is referred to as a cell region and a partial region B represents the cell region
40
. Moreover, a gate wiring region
4
is formed around the cell region
40
and a partial region A represents a boundary portion between the cell region
40
and the gate wiring region
4
.
FIG. 9
is an enlarged plan view showing patterns of various semiconductor layers exposed to the upper main surface of the semiconductor substrate
1
in the region A of FIG.
8
. Moreover,
FIG. 10
is a sectional view taken along a cutting line E—E in FIG.
9
. The semiconductor substrate
1
comprises an N
+
layer
11
exposed to a lower main surface, an N
−
layer
10
formed on the N
+
layer
11
, an N layer
17
having a low resistance which is formed on the N layer
10
and is exposed to the upper main surface, P base layers
6
,
7
and
8
selectively formed in the upper main surface, a P
+
base layer
20
having a low resistance which is protruded downward in central parts of bottom portions of the P base layers
6
and
7
, and an N source layer
5
selectively formed in the upper main surface more shallowly than the P base layer
6
on the inside thereof. The N layer
17
is formed more shallowly than the P base layers
6
,
7
and
8
.
The P base layers
6
and
7
have polygonal (square in the example of
FIG. 9
) planar shapes and are isolated from each other and arranged in a matrix. Moreover, the P base layers
6
and
7
are also isolated from the P base region
8
formed under the gate wiring region
4
.
The N source layer
5
formed in the P base layer
6
has an annular planar shape and forms the same polygon (square in the example of
FIG. 9
) as the P base layer
6
. An annular portion of the P base layer
6
positioned on the outside of the annular N source layer
5
functions as a channel region. On the other hand, the N source layer
5
is not formed in the P base layers
7
and
8
. Accordingly, the P base layers
7
and
8
do not have the channel region. The P base layer
7
is selectively formed in the vicinity of the P base layer
8
.
An insulating layer
15
is formed on the upper main surface of the semiconductor substrate
1
, and a source electrode
16
is formed on the insulating layer
15
. The source electrode
16
is covered with another insulating layer
30
. The P base layers
6
and
7
are connected to the source electrode
16
through an opening
9
selectively formed on the insulating layer
15
. The source electrode
16
is also connected to the P base region
8
through an opening
31
selectively formed on the insulating layer
15
. More specifically, the P base layers
6
,
7
and
8
isolated from each other in the semiconductor substrate
1
are connected to each other through only the source electrode
16
.
A gate electrode
14
is buried in the insulating layer
15
and is opposed to the upper main surface of the semiconductor substrate
1
with a gate insulating film
13
, which is a part of the insulating layer
15
, interposed therebetween. The gate electrode
14
is opposed to the channel region of the P base layer
6
and is also opposed to an exposed surface of the N layer
17
(the exposed surface also implies a portion exposed to the upper main surface of the semiconductor substrate
1
). Furthermore, the gate electrode
14
is opposed to a part of an exposed surface of the P base layer
7
and the almost whole region of an exposed surface of the P base region
8
. A portion in the gate electrode
14
which is opposed to the almost whole region of the exposed surface of the P base region
8
functions as a gate wiring.
A drain electrode
12
is connected to the lower main surface of the semiconductor substrate
1
. As shown in
FIG. 10
, the N
+
layer
11
is exposed to the lower main surface in the MOSFET. Therefore, the drain electrode
12
is directly connected to the N
+
layer
11
.
In the MOSFET having the above-mentioned structure, when a gate voltage which is equal to or higher than a threshold voltage is applied to the gate electrode
14
in a state in which a positive voltage is applied to the drain electrode
12
based on the source electrode
16
, an inversion layer is formed in the exposed surface of the P base region
6
positioned under the gate electrode
14
, that is, the channel region and a current flows through the inversion layer. In other words, the MOSFET is turned ON.
If the gate voltage to be applied to the gate electrode
14
is less than a threshold, the inversion layer is annihilated. Therefore, the MOSFET is brought into an OFF state. At this time, a drain voltage is held by a depletion layer extended from a PN junction between each of the P base layers
6
,
7
and
8
and the N
−
layer
10
in a reverse bias state toward the inside of the N
−
layer
10
.
When a positive voltage is applied to the source electrode
16
based on the drain electrode
12
in a state in which the source electrode
16
and the gate electrode
14
are short-circuited from each other, holes are injected from each of the P base regions
6
,
7
and
8
connected to the source electrode
16
into the N
−
layer
10
and an electrons are injected from the N
+
layer
11
joined with the drain region
12
to the N
−
layer
10
. Since the PN junction between each of the P base regions
6
,
7
and
8
and the N
−
layer
10
functions as a diode, a current flows from the source electrode
16
to the drain electrode
12
.
When a negative voltage is applied to the source electrode
16
based on the drain electrode
12
in this state, that is, a source-drain voltage is inverted into a reverse bias, the holes remaining in the N
−
layer
10
moves to the source electrode
16
and the electrons remaining in the N
−
layer
10
moves to the drain electrode
12
. As a result, a current flows from the drain electrode
12
to the source electrode
16
. A mobility of the hole is half of that of the electron. Therefore, a time required for attenuating the current to zero is equal to a time required for annihilating the holes remaining in the N
−
layer
10
. An operation of the MOSFET which is carried out under the reverse voltage is exactly equivalent to a recovery operation of a diode provided in the MOSFET.
A switching loss generated by a switching operation of the MOSFET greatly depends on a feedback capacitance, which is a parasitic capacitance of the MOSFET. The feedback capacitance is generated between the gate electrode
14
and the N layer
17
opposed thereto and greatly depends on an area of the exposed surface of the N layer
17
. In the conventional MOSFET, the P base layer
6
belonging to each cell is arranged in a matrix. As a result, there has been a problem in that an occupation ratio of the exposed surface of the N layer
17
is higher than that of the exposed surface of the P base layer
6
in the upper main surface of the semiconductor substrate
1
and the feedback capacitance is large.
Moreover, the P base layers
6
and
7
of the conventional MOSFET have polygonal planar shapes. Therefore, a distance between the P base layers
6
and
7
adjacent to each other in a direction of the matrix
Hatade Kazunari
Takano Kazutoyo
Huynh Andy
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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