Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S763000, C257S764000, C257S781000

Reexamination Certificate

active

06339257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly to a semiconductor device having a bonding pad electrode.
2. Description of the Background Art
Recently, as the integration degree of the semiconductor devices increases and the devices are provided with multiple functions, the interconnections thereof are increasingly fine patterned and formed with multiple layers. Thus, a multilayer interconnection technique is important. Such multilayer interconnection is connected to a bonding pad electrode, which is electrically connected to a lead pin by a bonding wire.
FIG. 8
is a cross sectional view showing a structure of a conventional bonding pad electrode. Referring to
FIG. 8
, an interlayer insulating film
102
is formed on a silicon substrate
101
. An interlayer insulating film
104
is formed on interlayer insulating film
102
. A large number of interconnection layers (not shown) are formed in interlayer insulating films
102
and
104
. A bonding pad electrode
106
which is electrically connected to these interconnection layers is formed on interlayer insulating film
104
. An interlayer insulating film
107
is formed on interlayer insulating film
104
to cover bonding pad electrode
106
. A via hole
105
is formed in interlayer insulating film
107
which exposes a part of a surface of bonding pad electrode
106
.
Recently, fine patterning is also required for such bonding pad electrode. Thus, a width and thickness of bonding pad electrode
106
as shown in
FIG. 8
are increasingly reduced.
FIG. 9
is a cross sectional view showing a bonding pad electrode shown in conjunction with a problem associated with the conventional bonding pad electrode. As shown in
FIG. 9
, in a conventional semiconductor device, a test called a wafer test is performed before dicing the wafer. A probe needle
112
generally including tungsten is brought into contact with a bonding pad electrode
106
for an electrical test. As a thin oxide film (Al
2
O
3
) is formed on a surface of bonding pad electrode
106
, a certain degree of load must be applied to probe needle
112
against bonding pad electrode
106
to break the oxide film, so that electrical conduction between bonding pad electrode
106
and probe needle
112
is ensured. At the time, no particular problem arises when a thickness of bonding pad electrode
106
is equal to or larger than 8000 Å. However, when the thickness of bonding pad electrode
106
is smaller than 8000 Å, an external force applied by probe needle
112
concentrates stress at one portion of interlayer insulating film
104
under bonding pad electrode
106
. Thus, a crack
111
appears in interlayer insulating film
104
.
FIG. 10
is a cross sectional view showing a bonding pad electrode shown in conjunction with a problem associated with connection of a bonding wire to the bonding pad electrode shown in FIG.
9
. Referring to
FIG. 10
, if a bonding wire
114
is connected to the bonding pad electrode on interlayer insulating film
104
in which the crack is formed as shown in
FIG. 9
, a cracked portion
113
is formed in bonding pad electrode
116
from crack
111
when connecting bonding wire
114
. Cracked portion
113
causes a problem of unstable electrical connection. Further, moisture entering from cracked portion
113
disadvantageously reduces resistance to moisture of the semiconductor device.
Conventionally, a semiconductor device in which a bonding pad electrode and an interconnection layer positioned thereunder are in direct contact with each other has also been known.
FIGS. 11
to
13
are cross sectional views showing a semiconductor device described in Japanese Patent Laying-Open No. 5-243320. Referring to
FIG. 11
, in the semiconductor device as a conventional example, a lower aluminum interconnection
206
is formed on an interlayer insulating film
205
. A lower via hole
211
leading to lower aluminum interconnection
206
is formed in interlayer insulating film
205
. A tungsten sidewall
212
is formed on a sidewall of lower via hole
211
. An upper aluminum interconnection
208
is formed as a bonding pad electrode in contact with tungsten sidewall
212
and lower aluminum interconnection
206
. An upper via hole
213
leading to upper aluminum interconnection
208
is formed in interlayer insulating film
205
. A tungsten sidewall
214
is formed in contact with a sidewall of upper via hole
213
and upper aluminum interconnection
208
.
Referring to
FIG. 12
, as another conventional example, a first aluminum interconnection
221
is formed in contact with an interlayer insulating film
220
. A lower via hole
203
leading to first aluminum interconnection
221
is formed in an interlayer insulating film
220
. A tungsten sidewall
224
is formed in contact with a sidewall of lower via hole
203
and first aluminum interconnection
221
. A second aluminum interconnection
222
is formed in contact with tungsten sidewall
224
and first aluminum interconnection
221
. An upper via hole
204
leading to second aluminum interconnection
222
is formed in interlayer insulating film
220
. A diameter of lower via hole
203
is larger than that of upper via hole
204
. A tungsten sidewall
225
is formed in contact with a sidewall of upper via hole
204
and second aluminum interconnection
222
. A third aluminum interconnection
223
is formed as a bonding pad electrode in contact with tungsten sidewall
225
and second aluminum interconnection
222
.
Referring to
FIG. 13
, in still another embodiment of a semiconductor device, a diameter of lower via hole
203
is smaller than that of upper via hole
204
. In this respect, it is different from the semiconductor device shown in
FIG. 12
in which the diameter of lower via hole
203
is larger than upper via hole
204
. Other parts of the structure are similar to those of the semiconductor device shown in FIG.
12
.
As the bonding pad electrode and the interconnection layer thereunder are directly in contact with each other as shown in
FIGS. 11
to
13
, the crack in the interlayer insulating film and the breakage of the bonding pad electrode as shown in
FIGS. 9 and 10
can be prevented to a certain extent.
However, the semiconductor devices shown in
FIGS. 11
to
13
still suffer from various problems. In the semiconductor device shown in
FIG. 12
, for example, as strengths of first to third aluminum interconnections
221
to
223
are relatively low, if an external force is applied to third aluminum interconnection
223
by a probe needle in a direction indicated by an arrow
301
, the external force concentrates stress at a portion
220
a
of interlayer insulating film
220
directly below third aluminum interconnection
223
. Thus, a crack is formed at portion
220
a
of interlayer insulating film
220
, whereby first to third aluminum interconnections
221
to
223
thereabove may be cracked.
Further, when the external force is applied to third aluminum interconnection
223
by the probe needle in a direction indicated by an arrow
302
, a crack is formed at a portion
220
b
of interlayer insulating film
220
directly below third aluminum interconnection
223
. The crack would also result in the problem described in conjunction with
FIGS. 9 and 10
.
In addition, when the probe needle is brought into contact with third aluminum interconnection
223
and then separated therefrom, third aluminum interconnection
223
may come off from second aluminum interconnection
222
as the probe needle and third aluminum interconnection
223
are in a tight contact. Thus, third aluminum interconnection
223
may come off from second aluminum interconnection
222
at an interface
222
a
, thereby disadvantageously causing a loose connection.
SUMMARY OF THE INVENTION
The present invention is made to solve the aforementioned problems. An object of the present invention is to provide a semiconductor device with high reliability capable of preventing cracking in a layer below an interconnection layer.
An

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