Semiconductor device

Details Semiconductor device Semiconductor device

2000-11-03

2002-09-17

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S226000

Reexamination Certificate

active

06452858

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and relates in particular to a semiconductor memory device. More particularly, this invention relates to a semiconductor memory device containing a highly integrated and highly reliable memory utilizing an amplifying memory cell.
2. Description of Related Art
The widely used dynamic random access memory (DRAM) is a single transistor cell utilized as a memory cell and consisting of a single transistor and a single capacitor. However in recent years, as MOS transistors (MOSFET: Metal Oxide Semiconductor Field Effect Transistor)in semiconductor devices become more highly integrated and more miniaturized, the breakdown voltage becomes lower and the operating voltage has also become lower to achieve lower electrical power consumption also becomes lower. In addition, in a DRAM utilizing a single transistor cell, the memory cell itself has no amplifying action so that the read out signal level from the memory cell is small and operation tends to be unstable because of effects from all types of noise.
So, a memory cell utilizing three transistors (hereafter three-transistor cell) and previously used prior to the single transistor cell is again attracting attention as a memory cell capable of delivering a large read-out signal level by an amplifying action. This three-transistor cell is described for instance in the IEEE International Solid-State Conference, DIGEST OF TECHNICAL PAPERS, pp. 10-11, 1972).
This memory cell for example as shown in
FIG. 2
, is comprised of a read-out NMOS transistor QR, a write NMOS transistor QW, and also a charge holding NMOS transistor QN. The gates of the transistors QR and QW are connected to the word line WL, and the source is connected to the data line DL. The gate of the transistor QN is connected to the drain of the transistor QW, and the source of the transistor QN is connected to the source line SL. The transistor QN, QR drains are also connected. Here, the threshold voltage VTW of the transistor QW is set higher than the threshold voltage VTR of transistor QR, and the data line voltage amplitude is equal to the supply voltage amplitude VDL. In a memory cell configured this way, the word line voltage for the write operation must be a high write voltage VW higher than the threshold voltage VTW, and this value is generally set higher than the supply voltage VDL. Also, the word line voltage for the read operation must be a read voltage VR higher than the threshold voltage VTR, and lower than the threshold voltage VTW and this value is generally set between the supply voltage level VDL and ground potential. Further, the standby state (non-select state) of the word line voltage must be lower than the word line voltage VTR and is set for example at ground potential VSS.
A device having an amplifying memory cell comprised of one capacitor and two transistors (hereafter called capacitive coupling 2-transistor cell) is described in IEEE ELECTRONICS LETTERS May, 13, 1999 Vol. 35 No. 10, pp. 848-850).
This memory cell as shown in
FIG. 3
, is comprised of a read NMOS transistor QR, a write transistor QW, and also a coupling capacitor Cc for controlling the voltage of the memory cell node N. The transistors QR and QW are in a stacked configuration so this device is characterized by a small surface area. A transistor utilizing the tunnel effect is used as transistor QW so the leak current is small. These components are connected as follows. One end of the capacitor Cc and the gate of transistor QW are connected to the word line WL, and the source of transistor QW is connected to bit line BL. The other end of the capacitor Cc and the drain of the transistor QW are connected to the gate of the transistor QR, and the memory cell node N thus formed. The source of the transistor QR is grounded, and the drain connected to the sense line SL. The word line voltage VW for writing and the word line voltage VR for reading are respectively set in this kind of cell, as described for the three-transistor cell shown in FIG.
2
.
However, in the standby state (non-select state), the voltage potential VN (H) for the standby state of the memory cell node N written at the supply voltage level VDL, must be a word line voltage at a lower voltage potential than VTR, for instance the standby voltage −VB must be set lower than the ground voltage VSS. Therefore, in the three-transistor cell and the capacitive coupling type 2-transistor cell as described above, the read and write operation is controlled by a read voltage VR and write voltage VW applied to one word line.
SUMMARY OF THE INVENTION
This invention therefore has the object of achieving a high speed, low current consumption, high integration DRAM for maintaining high reliability. This invention also has the object of providing a semiconductor device containing a highly integrated and highly reliable memory utilizing an amplifying memory cell.
More specifically, this invention is two aspects as described next. The first aspect is a sub-word driver to drive a sub-word line with a 3-value word line voltage, and also a DRAM utilizing this word driver. The second aspect is a high speed, low current consumption, high integration DRAM maintaining high reliability and eliminating the problem of breakdown voltage in MOS transistors with this sub-word driver.
Hereafter, the background of this invention is related in detail while referring to example of the prior art.
Along with the higher integration and lower power consumption of DRAM devices, the delay time in the word line has become a problem. As one means to resolve the delay time problem, a hierarchical word line structure to divide these word lines in order to reduce their capacitive load, drive each line with separate drivers installed on each line, and having drivers installed on the each of the divided word line WL has been proposed. A sub-word driver utilizing such a structure has been described in the European Solid-State Circuits Conference Digest of Technical Papers, pp. 131-134, September 1992.
The circuit structure is shown in FIG.
4
. The circuit structure SWD enclosed by dashed lines in
FIG. 4
is the area of the sub-word driver. A main word line MWLb is connected to the gates of they PMOS transistor Mp
1
and the NMOS transistor Mn
1
. A common word line FXb is connected to the gate of the NMOS transistor Mn
2
. A common word line FXt is connected to the source of the transistor Mp
1
, and the sources of the transistors Mn
1
and Mn
2
are grounded. The main word lines from the drains of the transistors Mp
1
, Mn
1
, Mn
2
connect to the branching sub-word line SWL.
The operation of the circuit of
FIG. 4
is next described by referring to FIG.
5
. When the main word line MWLb at the high level supply voltage VDL is driven to a low level, ground level VSS, the common word line FXt at ground potential VSS is driven to supply voltage level VDL so that as shown in
FIG. 4
, the transistor Mp
1
for the sub-word driver conducts and, the sub-word line SWL at ground potential VSS is driven to select status at supply voltage VDL. In this way, the voltage level of the sub-word line SWL of the prior art sub-word driver is driven to one of two levels: a high level or a low level.
As related above, a memory array using a three-transistor cell or capacitive coupling 2-transistor cell having low voltage operation, must set the word line to three values. Therefore, a sub-word driver capable of driving the sub-word line to voltage levels of three values is required in order to use this hierarchical word line structure. The gate oxidation film of the MOS transistors in the peripheral circuits should preferably be made thin to prevent a drop in MOS transistor performance even during low voltage operation. Due to these factors, the maximum permissible electric field of the oxidation film of the MOS transistors in the applicable peripheral circuits therefore tends to drop.
However, when a MOS transistor having the same tox oxidation film thickness tox, as the peripheral tr

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