Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-12-20
2002-07-02
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000, C257S784000, C257S786000, C257S750000
Reexamination Certificate
active
06414393
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with a multilayer wiring structure in which a plurality of layers are provided on a substrate and in which predetermined elements and a connection wiring for electrically connecting the elements are formed on each layer
In the recent years, the miniaturization of various types of wirings such as a connection wiring for mutually connection among the gate electrode of an MOS transistor, an ohmic electrode to elements and the elements, has progressed with the miniaturization of semiconductor element. As an internal structure of the semiconductor device capable of satisfying such miniaturization, a multilayer wiring structure which is a stacked structure, is widely employed. This multilayer wiring structure has advantages in that chip size can be made smaller, a LSI can be made further multifunctional and accelerated and the degree of freedom in circuit design can be improved. On the other hand, the multilayer wiring structure has disadvantages in that it has the difference in height between a portion which a connection wiring for mutually connecting elements exists and a portion on which no such connection wiring exists and the difference increases as connection wirings increasingly become multilayered. Such an increase of the difference in height may cause a malfunction such as, for example, the disconnection of a connection wiring formed or an upper layer. Conventionally, it is well known that a dummy pattern having almost the same height as that of a connection wiring is provided on a portion on which no connection wiring exists, so as to suppress the difference in height.
FIG. 7
shows one example of a dummy pattern formed on a conventional semiconductor device having a multilayer wiring structure. A dummy pattern
73
, which is almost as high as two connection wirings
72
a
and
72
b
formed on a substrate
71
and which is made of aluminum alloy, is provided so that the outer peripheral portion of the pattern
73
is adjacent to the connection wirings
72
a
and
72
b
. With this constitution, the difference in height between a portion on which the connection wirings
72
a
and
72
b
exist and a portion on which the connection wirings
72
a
and
72
b
do not exist can be suppressed. As a result, it is possible to avoid a malfunction such as the disconnection of a connection wiring (not shown) formed on an upper layer.
Meanwhile, the dummy pattern
73
is usually formed in a solid manner on a portion on which the connection wirings
72
a
and
72
b
do not exist. The area of the pattern
73
is considerably large compared with that of the connection wirings
72
a
and
72
b
. To constitute a multilayer wiring structure, patterning by means of exposure photolithography is repeated. If the connection wirings
72
a
,
72
b
and the dummy pattern
73
have such a relationship in size, a difference in surface reflection quantity occurs between the connection wirings and the dummy pattern during exposure. It is empirically known that the gap (space) between the connection wirings and the dummy pattern tends to be narrower than that between the connection wirings according to the difference in surface reflection quantity. If the gap is narrowed, short defects tends to occur between the connection wirings and the dummy pattern. If aluminum alloy is used as a material for the connection wirings, in particular, hillock (aluminum solid-phase growth) may possibly occur by a heat treatment during process. As a result, short defects may occur more frequently between the connection wirings and the dummy pattern.
Moreover, in the semiconductor device having the above-described multilayer wiring structure, a dummy pattern is normally in a floating state in which the dummy pattern is electrically isolated. In this state, the potential of the dummy pattern is unstable and there is near that wiring delay may occur to adjacent connection wirings due to the unstable potential.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above-stated technical disadvantages and it is, therefore, an object of the present invention to provide a semiconductor device capable of suppressing a short defect between a dummy pattern and a connection wiring.
It is another object of the present invention to provide a semiconductor device capable of ensuring the good potential stability of a dummy pattern.
To accomplish these objects, in a first aspect of the present invention, there is provided a semiconductor device having a multilayer wiring structure in which a plurality of layers are formed on a substrate and in which predetermined elements and a connection wiring for electrically connecting the predetermined elements are formed on each layer, characterized in that a dummy pattern almost as high as the connection wiring is provided in a predetermined region of each layer so that an outer peripheral portion of the dummy pattern is adjacent to the connection wiring; and the dummy pattern is formed linearly at least on the outer peripheral portion, and a distance between a linearly formed portion and a portion inside of the linearly formed portion is set to be equal to or narrower than a distance between the connection wiring and the linearly formed portion.
In a second aspect of the present invention, the dummy pattern has another linearly formed portion inside of the linearly formed portion on the outer peripheral portion.
Further, in a third aspect of the present invention, the dummy pattern is provided on both sides of an isolated connection wiring.
Moreover, in a fourth aspect of the present invention, constituent portions of the dummy pattern are connected to the substrate through conductive contacts, respectively.
Additionally, in a fifth aspect of the present invention, constituent portions of the dummy pattern are connected to a connection wiring formed on an upper layer of the layer on which the dummy pattern is formed, through conductive contacts, respectively.
REFERENCES:
patent: 6103626 (2000-08-01), Kim
Omae Tadashi
Shimizu Satoshi
Sumino Jun
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Thomas Tom
Tran Thien F
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