Semiconductor device

Details Semiconductor device Semiconductor device

2001-04-17

2002-05-14

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S798000, C438S401000

Reexamination Certificate

active

06388341

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 USC §119 to Japanese patent application No.2000-115120, filed on Apr. 17, 2000, the contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to a semiconductor device. More specifically, the invention relates to the structure of a semiconductor device which has an improved integration degree by improving the planarization of the device and the alignment precision during the production thereof.
2. Related Background Art
In order to scale down semiconductor devices, it is important to flatten the surfaces of semiconductor wafers and to improve the alignment precision between fabricating steps.
For example, as shown in
FIG. 6A
, if an underlayer
101
, on which a pattern is to be transferred, has a difference in level at a lithography step for fabricating a semiconductor device, a resist film
105
also has a difference in level, so that the focal position of exposure beams LB for transferring a pattern fluctuates. For example, if the focal position of exposure beams LB is matched with the portion having the difference in level, a normal pattern image Img
1
can be obtained thereon. However, the focal position is shifted on a flat portion so as not to normally form an image thereon, so that a transferred pattern image Img
2
′ is a pattern image which is out of focus. For that reason, if an underlayer pattern has a large number of differences in level, a fine pattern can not be transferred. Therefore, in order to obtain normal pattern images in all of regions to be transferred, it is necessary to flatten an underlayer pattern
103
as flat as possible as shown in, e.g.,
FIG. 6B
before the lithography step.
As planarization techniques, the chemical mechanical polishing (which will be hereinafter referred to as the “CMP”) technique is widely used in recent years. The CMP is a technique for applying a fine abrasive material on the surface of a wafer to mechanically polish the surface thereof.
However, in the polishing using the CMP, it is required to lubricatively supply the abrasive material between a smooth polishing plate and the surface of the wafer and to rapidly discharge polished waste materials from the surface of the wafer after the polishing. Therefore, when a large pattern is polished or when polishing is carried out in a wide area between patterns, the adhesion between the polishing plate and the surface of the wafer is too high, so that the supply of the abrasive material and the discharge of the polished waste materials are obstructed. For that reason, it is difficult to carry out a good polishing. In addition, if a pattern, only a small part of which has a protruding portion, is polished, the polishing force concentrates on the protruding pattern, so that the polishing rate remarkably increases, thereby being difficult to control the quantity of polished materials. For that reason, in order to improve the polishing precision using the CMP, the maximum size of a pattern to be polished and the ratio of irregularities must be appropriately set.
Therefore, it is important to closely arrange patterns while adjusting the ratio of irregularities of the patterns.
FIGS. 7A and 7B
are schematic sectional views for explaining the need for closely arranging patterns on the surface of a wafer. As shown in
FIG. 7A
, when only one transistor is intended to be formed, only a transistor forming pattern PT
1
protrudes with respect to a surrounding wide element isolating region
110
. However, as shown in
FIG. 7B
, if a pattern PT
2
is arranged so as to be close to the pattern PT
1
the ratio of protruding portions in the surface region, so that it is possible to set an appropriate quantity for processing.
A conventional aligning method between fabricating steps will be described below.
FIG. 8A
is an illustration for explaining a conventional aligning method. Furthermore, in the following drawings, the same reference numbers are given to the same portions, and the detailed descriptions thereof are omitted.
An alignment mark
50
includes three linear patterns Pa
1
through Pa
3
which are arranged in parallel to each other. With respect to these linear patterns, an optical image using an optical microscope or an electron diffraction image using a scanning electron microscope is acquired in a range extending perpendicularly to the respective lines as shown in a region Rp
50
, to obtain light intensities or electron beam intensities, a profile of
FIG. 8B
is obtained. It can be seen from
FIG. 8B
that an intensity distribution corresponding to the arrangement of the respective patterns Pa
1
through Pa
3
is obtained. Defining the intensity peaks corresponding to the patterns Pa
1
through Pa
3
as Sa
1
through Sa
3
, respectively, defining the distance between the patterns Sa
3
and Sa
1
as d
1
and defining the distance between the patterns Sa
3
and Sa
3
as d
2
, these distances correspond to pitches between the respective patterns, respectively. When three lined-up peaks, the distances between which are d
1
and d
2
in order from the left in
FIG. 8B
, are observed, if it is previously registered in a pattern recognition system that the central peak is set as the origin in alignment, it is possible to carry out an alignment between the current step and the last step.
In order to carry out the CMP of a device including alignment marks shown in
FIG. 8A
, it is difficult to apply the CMP with respect to both of a too broad pattern and a too wide space, some pattern must be arranged around the alignment marks.
FIG. 9A
shows an example of a semiconductor device in which patterns including such a CMP processing dummy pattern are arranged. The dummy pattern is arranged for the main purpose of improving the CMP processing precision, and plays little part in the operation of the device. Furthermore, in place of the dummy pattern, a pattern playing some part in the operation of the device may be arranged to enhance the CMP processing precision.
In a semiconductor device shown in
FIG. 9A
, dummy patterns Pd are arranged from a position, which is spaced from the line patterns Pa
1
in an alignment mark
60
by a distance d
2
, in a region Rc
60
having an appropriate set size, and periodically arranged in a cycle d
1
in lateral directions of the figure.
If the light intensity or electron beam intensity of the patterns is derived in the same manner as the method shown in
FIG. 8B
, a profile of
FIG. 9B
is obtained. A combination of three lined-up peaks, the distances between which are d
1
and d
2
in order from the left of the figure, is extracted from a profile of
FIG. 9B
, it is possible to fine two combinations, i.e., a combination SET
1
based on the original alignment mark
60
, and a combination SET
2
based on the dummy patterns and a part of the alignment mark
60
. This shows that there is some possibility that the origin is set at an erroneous place, such as the SET
2
, if the alignment is carried out using the pattern arrangement shown in FIG.
9
A. This causes a problem in that the alignment precision is remarkably deteriorated.
Although false recognition from the surrounding dummy patterns can be prevented if the alignment marks are further complicated, the recognizing procedure is more complicated than the procedure for identifying the alignment mark itself, so that the costs of the identifying system are increased and the alignment rate is decreased, thereby increasing the whole manufacturing costs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor device capable of improving an alignment precision while further developing the scale down of a device by flattening the device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: first patterns for alignment which are arranged in a first region on the surface of a semiconducto

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