Semiconductor device

Details Semiconductor device Semiconductor device

2001-07-13

2002-05-14

Mai, Son L. (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S200000, C365S225700, C365S189070, C365S185090

Reexamination Certificate

active

06388941

ABSTRACT:

BACKGROUND
The present invention relates to a technology of relieving a defect of a memory, and particularly to a semiconductor device capable of relieving defects at a probe test stage of the semiconductor device and after its assembly through the use of both of two types of memory elements different in element structure. The present invention also relates to a technology effective for application to a DRAM (Dynamic Random Access Memory), for example.
Unexamined Patent Publication No. Hei 8(1996)-31196 discloses defective address memory means which utilizes an element M1
and a fuse F1 in combination. Unexamined Patent Publication No. Hei 8(1996)-255498 discloses a first redundant address storage circuit 26 including a laser program circuit 40a, and a second redundant address storage circuit 28 including an electrically programmable circuit 42a. Unexamined Patent Publication No. Hei 7(1995)-326198 discloses the technology of storing a defective cell address in a second defective cell address memory 7 by electrical redundancy when a defect occurs in a first defective cell address memory 5 due to laser redundancy. Unexamined Patent Publication No. Hei 3(1991)-157897 (corresponding U.S. Pat. No. 5,233,566) discloses a fuse 5 corresponding to memory means for storing information used for substitution of an abnormal cell with another by non-electrical means, and an n channel FAMOS which is an EPROM cell transistor corresponding to means for storing information used for substitution with a redundant cell by electrical means. Unexamined Patent Publication No. Hei 1(1989)-261845 (corresponding U.S. Pat. No. 5,018,104) discloses a redundant circuit including a first switch element including a non-volatile memory cell provided with means for avoiding erasure, and a second switch element capable of being reset to a pre-switching state. Unexamined Patent Publication No. Hei 4(1992)-328398 (corresponding U.S. Pat. No. 5,319,599) discloses a redundant circuit including a first switch element comprised of a non-volatile memory cell, and a second switch element comprised of an element capable of freely writing and erasing data of an EPROM or the like. Unexamined Patent Publication No. Hei 11(1999)-16385 discloses a semiconductor memory device including a spare column (row) decoder for polysilicon, and a spare column (row) decoder for UPROM (unerasable PROM). Unexamined Patent Publication No. Hei 8(1996)-335674 discloses a method of trimming a semiconductor device wherein, of a plurality of circuits having different functions or characteristics, disposed between main lines of a semiconductor integrated circuit device, one circuit or two or more circuits are selectively connected to the main lines.
SUMMARY OF THE INVENTION
In a process for manufacturing a memory such as a DRAM or the like, defective bits have been relieved upon a wafer probe test. However, defects might take place newly in its subsequent aging or assembly process. Further, defective bits might be left because a relieving process is improper. It is necessary to allow relieving even after the assembly. Therefore, a discussion has been made of a case in which two types of fuses are mounted and an electric fuse relievable after assembly is used as one of them. As the two types of fuses, may be mentioned, a cutoff type laser fuse, an electrically programmable memory device or element (electric fuse) like an EPROM memory cell.
The present inventors have made a discussion about the mounting of electric fuses on a semiconductor device for the purpose of defect relief. According to the discussion, a by-chip occupied area based on electric fuses, latch circuits attendant on them, etc. becomes greatly larger than a by-chip occupied area based on cutoff type laser fuses, and latch circuits attendant on them. When all is comprised of the electric fuses, an area penalty excessively increases. Therefore, if logic circuit portions subsequent to latch circuits attendant on the cutoff type and electric fuses are dedicated for the respective fuses and made attendant thereon when an attempt is made to utilize the cutoff type and electric fuses in combination, it became evident that the area penalty excessively increased after all. The present inventors have found that when the cutoff type and electric fuses are utilized in combination, it is necessary to reduce a by-chip occupied area using or based on address wirings for supplying address information to the respective fuses and signal wirings for transferring the result of comparison, as small as possible.
The known reference has no described the standpoint that an increase in the by-chip occupied area at the time that both the electric and cutoff type fuses are used, is reduced to the utmost.
An object of the present invention is to reduce an increase in by-chip occupied area due to memory elements different in element or device structure as typified by electric and cutoff type fuses, as small as possible from a layout viewpoint when the memory elements are used to hold address information for relief.
Another object of the present invention is to improve the reliability of long-term data retention when an electric program holds address information for relief.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] A semiconductor device has a first memory array unit in which normal memory cell are disposed, and a second memory array unit in which redundant memory cell are disposed. Address information of memory cells to be relieved in the first memory array unit are stored in a plurality of first memory elements and second memory elements different in element structure from one another. A plurality of first comparators respectively compare the address information stored in the first memory elements with signal information on an address signal wiring. A plurality of second comparators compare the address information stored in the second memory elements with signal information on the address signal wiring. A relief control circuit performs control for switching an access to the first memory array unit to an access to the second memory array unit according to the coincidence between the results of comparisons by the first and second comparators. The plurality of first memory elements and first comparators are formed in a first area along the address signal wiring, and the plurality of second memory elements and second comparators are formed in a second area adjacent to the first area.
The first memory elements are, for example, cutoff type fuses (cutoff fuse) which store information according to the presence or absence of cutoff. The second memory elements are, for example, electrically programmable non-volatile memory elements (electric fuses) which store information according to a difference in threshold voltage.
The first area and the second area are allocated along the address signal wiring and they are disposed so as to adjoin each other. Therefore, even if the memory elements different in device structure or circuit configuration are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.
As a desirable form, the address signal wiring may be shared between the first comparators and the second comparators. Since the first comparators and the second comparators may be disposed along the address signal wiring, there is no necessity to separately provide them. Sharing the address signal wiring therebetween allows restraint on an increase in by-chip occupied area.
As a desirable form, the address signal wiring may be provided so as to linearly cross over a portion where the fir

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