Semiconductor device

Details Semiconductor device Semiconductor device

2000-06-28

2002-04-23

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S158000

Reexamination Certificate

active

06377100

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a stabilized timing circuit (STC), such as a delayed locked loop (DLL), for regulating the phase of two external clocks constituting complementary clocks input from an external source and generating internal clocks having a predetermined phase relationship with the two external clocks. More specifically, the present invention relates to a synchronous dynamic random access memory (hereinafter, abbreviated to SDRAM) for generating internal clocks delayed by a predetermined phase from external clocks supplied from an external source in a complementary clock form (i.e. differential clock form) regardless of the fluctuations of the ambient temperature, the source voltage, and the like.
In recent years, a higher speed of the SDRAM has been required with an increase in a speed of a CPU (central processing unit). In order to meet this requirement, a sufficient data window representing the data available time is required to be secured while reducing the clock cycle time. For this purpose, it is necessary to accurately control the timing of the data output and to secure a sufficient margin to retrieve the address and data by using an STC such as a DLL circuit.
2. Description of the Related Art
Generally, in an SDRAM operating at high speed, it is necessary that data are always input and output correctly and in a predetermined accurate phase relationship (for example, at 360° corresponding to one period of the clock, or in another phase relationship) with an external clock input from an external source. Usually, therefore, the SDRAM includes a DLL circuit or the like to accurately regulate the phase difference between the clock input from an external source and an internal clock and to generate the internal clock, so that the external clock input to the DLL circuit is apparently in phase with the data output from the SDRAM.
The data is input to and output from the SDRAM, according to the related art, in synchronism with the leading (or trailing) edge of the external clock and, therefore, the maximum frequency of the data is limited to the same frequency as the external clock. To address this disadvantage, a technique (e.g., DDR (double data rate)) has been developed, in which a data signal is input and output in synchronism with both the leading edge of a first clock input from an external source and the leading edge of a second clock complementary with the first clock (i.e., second clock which is out of phase with the first clock by 180°). In other words, the data can be input and output at a transfer rate twice as high as the case in which only one of the edges of the clocks is used. For this purpose, a DLL circuit has been proposed which is supplied with first and second clocks complementary with each other and generates first and second internal clocks in phase with the first and second clocks, respectively, that is to say, which operates in the complementary clock form.
To facilitate understanding of the problem concerning a conventional STC such as an ordinary DLL circuit operating in the complementary clock form, the configuration of a clock circuit according to the related art will be explained with reference to
FIG. 1
described later in “BRIEF DESCRIPTION OF THE DRAWINGS”.
A configuration of the STC according to the related art, operating in the complementary clock form for outputting complementary internal clocks, is illustrated in FIG.
1
. As shown in
FIG. 1
, a STC
100
is typically configured with a DLL circuit for outputting first and second internal clocks complementary with each other in phase with the leading edge of two external clocks (a first clock CLK and a second clock /CLK) complementary with each other. By way of explanation, each of the external clocks will be referred to merely as “clock”.
The DLL circuit shown in
FIG. 1
includes a clock input circuit unit
200
supplied with two external clocks complementary with each other (for example, a first clock CLK and a second clock /CLK which is out of phase with the first clock CLK by 180°). The clock input circuit unit
200
in turn includes a first input first stage circuit unit
200
a
and a second input first stage circuit unit
200
b
for generating two input clocks complementary with each other (for example, a first input clock clkz and a second input clock clkbz which is out of phase with the first input clock clkz by 180°) based on the first clock CLK and the second clock /CLK, respectively.
Further, the DLL circuit shown in
FIG. 1
includes a first delay element circuit unit
300
a
and a second delay element circuit unit
300
b
for delaying, by a predetermined phase, the two input clocks clkz, clkbz supplied from the first input first stage circuit unit
200
a
and the second input first stage circuit unit
200
b,
respectively; and a delay element control circuit unit
400
for setting a delay amount (delay time) corresponding to the delay of a predetermined phase from the external clocks by controlling the number of delay stages of the first and second delay element circuit units
300
a,
300
b.
Further, the DLL circuit shown in
FIG. 1
includes a frequency divider
800
for generating a reference clock refclk by dividing the frequency of the first input clock clkz; and a phase comparing unit
900
for comparing the phase of the reference clock refclk supplied from the frequency divider
800
with the phase of the dummy clock dumclk
3
output from a dummy circuit
600
described later. The delay element control circuit unit
400
sets the delay amount of the first and second delay element circuit units
300
a,
300
b
(and a dummy delay element circuit unit
630
described later) based on a phase difference signal pcclk obtained as the result of phase comparison, by the phase comparing unit
900
, between the reference clock refclk and the dummy clock dumclk
3
.
Further, the DLL circuit shown in
FIG. 1
includes an output circuit unit
500
for retrieving the data DATA at the leading edge of each of the two internal clocks (for example, the first internal clock clkd and the second internal clock clkbd) output from the first and second delay element circuit units
300
a,
300
b,
respectively, and outputting the data DATA as output data (output signal Dout). The delay time is regulated by the first and second delay element circuit units
300
a,
300
b
in such a manner as to output the data from the data (output signal Dout) from the output circuit unit
500
in synchronism with the leading edge of the external clocks (CLK, /CLK) regardless of the fluctuations of the ambient temperature and the source voltage.
Further, the DLL circuit shown in
FIG. 1
includes a dummy circuit
600
for monitoring the time in which the external clocks pass through the clock input circuit unit
200
and the time in which the internal clocks pass through the output circuit unit
500
, in order to accurately set the delay amount corresponding to the phase delay of the internal clocks with respect to the external clocks. The dummy circuit
600
is configured with a dummy delay element circuit unit
630
which is set to have the same delay amount as each of the first and second delay element circuit units
300
a,
300
b
by means of the delay element control circuit unit
400
; a dummy input circuit unit
640
having the same delay amount as the clock input circuit unit
200
; and a dummy output circuit unit
650
having the same delay amount as the output circuit unit
500
.
The dummy clock dmuclk
1
output from the dummy delay element circuit unit
630
is output as a dummy clock dumclk
2
delayed by the delay amount of the output circuit unit
500
by the dummy output circuit unit
650
, and further delayed into a dummy clock dumclk
3
by the delay amount of the clock input circuit
640
by the dummy input circuit unit
640
. The dummy clock dumclk
3
corrected in this way is input to one of the input portions of the phase comparing unit
900
. On the other hand, the frequency of the first inpu

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