Semiconductor device

Details Semiconductor device Semiconductor device

1999-07-30

2002-01-01

Abraham, Fetsum (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S676000, C257S693000, C257S781000, C257S774000, C257S778000, C257S736000, C257S731000

Reexamination Certificate

active

06335565

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device wherein a plurality of types of semiconductor chips are held in a single package from an MCM (Multi Chip Module)-based approach so that signals can be inputted thereto and outputted therefrom with respect to each other, and particularly to a technique effective for application to a semiconductor device wherein a microcomputer including a CPU (Central Processing Unit), a programmable non-volatile memory such as a flash memory or the like, a DRAM (Dynamic Random Access Memory), and a logic LSI such as an ASIC (Application Specific Integrated Circuit) or the like are brought into one package.
BACKGROUND ART
The present inventors have discussed a technique wherein in a semiconductor device about a system on-chip, a plurality of types of semiconductor chips are accommodated or held in a single package so as to be able to input signals thereto and output the same therefrom with respect to each other from an MCM-based approach without bringing all of a microcomputer, a flash memory, a DRAM, an ASIC, etc. into one chip upon implementation of an approach to a DRMA/SIMM (Single In-line memory Module) having the high needs of users and a flash memory/DRAM-based microcomputer on-chip. The following is the corresponding technique discussed by the present inventors. Its summary is as follows:
A move attempt to form a microcomputer, a flash memory, a DRAM, an ASIC, etc. on one chip thereby to achieve the speeding up of a data transfer rate, space saving (improvements in packing density), low power consumption, etc. has recently been made active in front end technology such as a multimedia, information communications, etc. However, the formation of such many kinds of LSIs on one chip will cause an extreme increase in the load on a semiconductor manufacturing process.
This reason will be described below based on a process for placing or forming the microcomputer, flash memory, DRAM and ASIC in mixed form, which has been discussed by the present inventors. A summary of the mixed-loading process is as follows:
A p-type impurity (boron) is ion-implanted in a principal surface of a semiconductor substrate
100
to form a p well
101
as shown in FIG.
78
. Thereafter, a field oxide film
102
is formed over the surface of the p well
101
by a LOCOS method. An element or device formed at the left end in the drawing is a MOSFET which constitutes each memory cell of a DRAM, devices formed at a position adjacent to the right side are a MOSFET which constitutes each memory cell of a flash memory and a MOSFET for a high voltage, which constitutes part of a peripheral circuit of the flash memory. A device formed at the right end is a MOSFET which constitutes a logic LSI such as a microcomputer, an ASIC or the like. Incidentally, an actual LSI is comprised principally of an n channel MOSFET and a p channel MOSFET. However, only a region for forming the n channel MOSFET will be illustrated to simplify its description.
Next, a tunnel oxide film
103
for the flash memory is formed as shown in FIG.
79
. The thickness of the tunnel oxide film
103
is set so as to range from about 8 nm to 13 nm.
Next, as shown in
FIG. 80
, a polycrystal silicon film deposited on the semiconductor substrate
100
by CVD is subjected to patterning to form a floating gate
104
(part thereof) for the flash memory. Thereafter, a silicon oxide film, a silicon nitride film and a silicon oxide film are layered over the floating gate
104
as shown in
FIG. 81
thereby to form a second insulating film (ONO film)
105
whose thickness ranges from about 10 nm to 30 nm.
Next, a gate oxide film
106
for the MOSFET which withstands a high voltage, is formed in a peripheral circuit region of the flash memory as shown in FIG.
82
.
The gate oxide film
106
is formed to a thickness (which ranges from 10 nm to 30 nm) thicker than the thicknesses of gate oxide films for other MOSFETs.
Next, a gate oxide film
107
for the MOSFET which constitutes the logic LSI, and a gate oxide film
130
for the MOSFET which constitutes each memory cell for DRAM, are formed as shown in FIG.
83
. The thickness of the gate oxide film
107
is set so as to range from about 4 nm to 10 nm, whereas the thickness of the gate oxide film
130
is set so as to range from about 8 nm to 15 nm.
Next, as shown in
FIG. 84
, the polycrystal silicon film deposited over the semiconductor substrate
100
by CVD is subjected to patterning thereby to simultaneously form gate electrodes (word lines) for each individual memory cells of the DRAM, a control gate
109
for the flash memory, a gate electrode
110
for the high-withstand MOSFET, a gate electrode
111
for the MOSFET which constitutes the logic LSI. Thereafter, the (partly-formed) floating gate
104
for the flash memory is subjected to patterning to form a floating gate
104
as shown in FIG.
85
.
Next, n-type impurities (phosphorus and arsenic) are ion-implanted in part of a memory cell region of the flash memory as shown in
FIG. 86
to form an n
+
-type semiconductor region
112
for the flash memory. Thereafter, the n-type impurities (phosphorus and arsenic) are ion-implanted in part of the memory cell region of the flash memory, the peripheral circuit region thereof and a logic LSI forming region as shown in
FIG. 87
thereby to simultaneously form n
−
-type semiconductor regions
113
and
113
for the flash memory, n
−
-type semiconductor regions
113
and
113
for the high-withstand MOSFET, and n
−
-type semiconductor regions
113
and
113
for the MOSFET which constitutes the logic LSI.
Next, as shown in
FIG. 88
, side wall spacers
114
are respectively formed over the side walls of the gate electrodes (word lines)
108
for each individual memory cells of DRAM, the control gate
109
for the flash memory, the gate electrode
110
for the MOSFET for a high voltage, and the gate electrode
111
for the MOSFET which constitutes the logic LSI.
Next, the n-type impurities (phosphorus and arsenic) are ion-implanted in part of the memory cell region of the flash memory, the peripheral circuit region and the logic LSI forming region as shown in
FIG. 89
to simultaneously form an n
+
-type semiconductor region
115
for the flash memory, n
+
-type semiconductor regions
115
and
115
for the high-withstand MOSFET, and n
+
-type semiconductor regions
115
and
115
for the MOSFET which constitutes the logic LSI, whereby one of a source region and a drain region for the flash memory, a source region and a drain region for the high-withstand MOSFET, and a source region and a drain region for the MOSFET constituting the logic LSI are brought to an LDD (Lightly Doped Drain) structure.
Next, as shown in
FIG. 90
, a silicon oxide film
116
deposited over the semiconductor substrate
100
by CVD is etched to define connecting holes on both sides of the gate electrodes (word lines) of the DRAM and define a connecting hole in an upper portion of the n
+
-type semiconductor region
112
for the flash memory. Thereafter, plugs
117
each composed of a polycrystal silicon film are formed inside these connecting holes. On both sides of the gate electrodes of the DRAM, n-type semiconductor regions
118
are formed by impurities diffused from the polycrystal silicon film. Thereafter, the polycrystal silicon film deposited over the silicon oxide film
116
by CVD is subjected to patterning to form each bit line BL for the DRAM and each bit line BL for the flash memory.
Next, a silicon oxide film
119
is deposited over the semiconductor substrate
100
by CVD as shown in FIG.
91
. Thereafter, a polycrystal silicon film deposited over the silicon oxide film
119
is subjected to patterning to form lower electrodes
120
of capacitors for the DRAM.
A tantalum oxide film (or nitride silicon film) and the polycrystal silicon film deposited over the semiconductor substrate
100
are patterned to form an capacitive insulating film
121
and an upper electrode
122
of each capacitor for the DRAM as shown in FI

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