Semiconductor device

Details Semiconductor device Semiconductor device

2008-01-29

2008-01-29

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S700000, C257SE23169

Reexamination Certificate

active

07323773

ABSTRACT:
There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

REFERENCES:
patent: 6960827 (2005-11-01), Nishimura et al.
patent: 2001/0013653 (2001-08-01), Shoji
patent: 2004/0036170 (2004-02-01), Lee et al.
patent: 2004/0235287 (2004-11-01), Inoue et al.
patent: 10-12809 (1998-01-01), None
patent: 2004-022664 (2004-01-01), None
patent: WO 02/103793 (2002-12-01), None

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