Semiconductor device

Details Semiconductor device Semiconductor device

2011-03-01

2011-03-01

Parker, Kenneth A (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S774000, C257S773000, C257S751000, C257S762000

Reexamination Certificate

active

07898084

ABSTRACT:
A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection.

REFERENCES:
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Yao, et al., “Numerical Characterization of the Stress Induced Voiding Inside Via of Various Cu/Low k Interconnects”, Advanced Module Technology Division, R&D, Taiwan Semiconductor Manufacturing Co., Ltd., pp. 1-3, (2004).
Office Action from Japanese Patent Office mailed on May 19, 2009 for counterpart Japanese Patent Application No. 2005-010732.
Notice of Reasons for Rejection dated Mar. 17, 2010, from Japanese Patent Office in corresponding Japanese application No. 2005-010732.

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