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357 22, 357 55, 357 56, 357 58, 357 90, H01L 2778

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042439973

ABSTRACT:
The first and second intrinsic semiconductor layers of thickness d are formed on a P type semiconductor substrate, keeping a prescribed interval therebetween, whereby a groove of depth d may be made between these layers. A dielectric layer is formed in such a way that it may cover a base and sides of the groove and a surface of the intrinsic semiconductor layer. On this surface, a gate electrode formed of polysilicon exists. Diffusion regions of a source and a drain of depths X.sub.sj and X.sub.dj are formed, in the neighborhood of groove sides, in the first and second intrinsic semiconductor layers (X.sub.sj, X.sub.dj d), resulting in an MOS transistor.

REFERENCES:
patent: 3975221 (1976-08-01), Rodgers
patent: 4003126 (1977-01-01), Holmes et al.
Ames et al.-IBM Tech. Bul.-vol. 9, No. 1, Jun. 1976.

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