Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-04-11
2001-10-02
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S109000, C438S654000
Reexamination Certificate
active
06297073
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a resin sealed type semiconductor device and its mounting structure and in particular to a semiconductor device in which the external size of its package is very approximate to that of the semiconductor chip and its mounting structure.
With an advance in high integration of the semiconductor devices, a technology to provide semiconductor devices in which the size of the package for the semiconductor device is close to that of the chip has been developing. There are two approaches in this technology. One of the approaches is referred to as bare chip mounting in which a semiconductor chip is directly mounted on a printed circuit board (PCB) and is sealed with a resin.
The other approach is generally referred to as CSP (chip size package or chip scale package) in which the package which is resin sealed similarly to prior art is reduced to the size of the chip as small as possible.
A prior art structure of the CSP in which a tape with external terminals is provided on a circuit forming surface of a semiconductor chip so that a flexible material (elastomer resin) is interposed therebetween and the external terminals are electrically connected to the electrodes of the semiconductor chip is disclosed in JP-A-6-504408 (PCT Application) which was filed by Tessera Co., Ltd. Another prior art structure in which a semiconductor chip is mounted on a ceramic substrate having through-holes therein, which is provided on the side opposite to the chip with electrodes and is mounted on a PCB is disclosed in JP-A-6-224259. A further prior art structure of the CPS in which a semiconductor chip is formed on its circuit forming surface with metal wiring patterns, which are provided with external terminals is disclosed in JP-A-6-302604.
SUMMARY OF THE INVENTION
It is object of the present invention to provide a CSP type semiconductor device in which a high reliability is provided by reducing the thermal fatigue of both solder bumps and inner leads.
The external terminals of the CSP include metal bumps which are arrayed in the form of grating and are connected to a PCB. The bumps are most commonly formed of solder. The greatest problem which occurs in the CSP having such a structure is the reliability of connection of solder bumps. If the linear expansion coefficient of a semiconductor chip is largely different from that of a PCB, stress occurs in the bumps with changes in temperature. Repetition of this stress may damage the device due to thermal fatigue.
It is deemed that the semiconductor device disclosed in JP-A-6-504408 is highest in reliability among the prior art structures since it most takes the fatigue damage of the solder into consideration. In this semiconductor device, a tape is provided on a circuit forming surface a semiconductor chip in such a manner that a flexible elastomer resin portion is interposed therebetween and a wiring pattern formed of a metal foil which are continuous to leads are adhered to the tape. The terminals of the leads are bonded to the electrodes of the semiconductor chips. These bonding portions are sealed with a seal resin. Metal bumps are bonded to the wiring patterns and are bonded on the opposite side to wiring patterns formed on a PCB. A mounting structure is thus formed. Since the tape having metal bumps is provided on the circuit forming surface of the semiconductor chip so that the flexible elastomer resin is disposed therebetween in this type of semiconductor device, the difference between the linear expansion coefficient of the semiconductor chip and that of the PCB is absorbed by the shear deformation of the flexible elastomer resin. As a result, no stress is applied to the metal bumps.
However, another problem occurs in this type of semiconductor device due to the fact that the elastomer resin is flexible. The leads which electrically connect the electrodes of the semiconductor chips to the metal bumps extend through the elastomer resin in a depth direction. Accordingly, the fact that the difference between the linear expansion coefficient of the semiconductor chip and that of the PCB is absorbed by the shear deformation of the elastomer resin means that the leads are also similarly deformed. Although the metal bumps have a high reliability, the leads may be broken due to fatigue. Ultimately, this may cause a failure of the semiconductor device.
The bonding portions between the electrodes of the semiconductor device and the leads are sealed with a resin which is flexible as similarly to the elastomer resin. A resin which are flexible, that is, has a low modulus of elasticity generally has a high linear expansion coefficient. The difference between the thermal expansion coefficient of the resin and that of the leads themselves is large. This may cause the leads to be damaged due to thermal fatigue.
The above-mentioned prior art structure type CSP has a problem in either of the reliability of the solder bumps or the reliability of the inner leads and does not have enough reliability as a whole. In accordance with the present invention, a CSP type semiconductor device which overcomes the drawbacks of the prior art CSP and has a high reliability in both solder bumps and inner leads is implemented.
The object of the present invention is achieved by a semiconductor device, comprising semiconductor chips, elastomer resin portion which are bonded to said semiconductor chip excepting at least some of a plurality of electrode of said semiconductor chips, a resin tape layer which is connected to said elastomer resin portion and is provided with wiring patterns on the surface thereof and a plurality of solder bumps which are bonded to the wiring patterns on said resin tape layer, said wiring patterns of said resin tape layer being connected to the plurality of electrodes of said semiconductor chip, connection portions between the wiring patterns of said resin tape layer and the electrodes of said semiconductor chips being sealed with a seal resin, in which the modulus of the elastomer resin portions and the linear expansion coefficient of the lead sealing resin is optimized.
The semiconductor device of the present invention is characterized in that (1) said elastomer resin portion has a modulus of transverse elasticity of not less than 50 MPa and not more than 750 MPa, (2) said elastomer resin portion has a modulus of longitudinal elasticity of not less than 150 MPa and not more than 2250 MPa, or (3) said seal resin has a linear expansion coefficient of not more than 100×10
−6
/° C. The mounting structure of the present invention is characterized in that the semiconductor device as defined in any of (1) to (3) is mounted on a PCB of glass cloth epoxy resin.
As mentioned above, in accordance with the present invention, the deformation due to the difference between the linear expansion coefficient of the semiconductor chip and that of the PCB is shared by the elastomer resin portion and the solder bumps in a well balanced manner. Accordingly, stress in both the solder bumps and the inner leads due to changes in temperature can be reduced so that the reliability of the CSP type semiconductor device can be largely enhanced.
REFERENCES:
patent: 5346861 (1994-09-01), Khandros et al.
patent: 5576630 (1996-11-01), Fujita
patent: 5726075 (1998-03-01), Farnworth et al.
patent: 5737191 (1998-04-01), Horiuchi et al.
patent: 5789809 (1998-08-01), Joshi
patent: 5885849 (1999-03-01), DiStefano et al.
patent: 5994168 (1999-11-01), Egawa
patent: 210371 (1987-02-01), None
patent: 6-224259 (1994-08-01), None
patent: 6-302604 (1994-10-01), None
patent: 6-504408 (1998-05-01), None
Anjoh Ichiro
Eguchi Shuji
Kitano Makoto
Kohno Ryuji
Kumazawa Tetsuo
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Potter Roy
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2588286