Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1998-08-05
2001-10-23
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S289000, C257S327000
Reexamination Certificate
active
06307220
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention disclosed in the specification relates to a semiconductor device utilizing crystalline semiconductor, particularly to the constitution of an insulating gate type transistor. Further, the present invention relates to the constitution of a semiconductor circuit and an electrooptical device comprising such a transistor or the like and an electronic instrument compounded with these.
Further, in the specification, all of a transistor, a semiconductor circuit, an electrooptical device and an electronic instrument are dealt with by including them in the category of “semiconductor device”. That is, all of devices capable of functioning by utilizing properties of a semiconductor are referred to as semiconductor devices. Accordingly, semiconductor devices described in the scope of claims include not only a single body of a transistor or the like but a semiconductor circuit and an electrooptical device integrated with these and an electronic instrument.
2. Description of Related Art
In the current state of VLSI (Very Large Scale Integrated Circuit) and ULSI (Ultra Large Scale Integrated Circuit), the element size tends to be more and more miniaturized in pursuit of promoting a further degree of integration. The trend is observed similarly in MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a bulk single crystal and TFT (Thin Film Transistor) using a thin film. Currently, there has been requested an element having a channel length of 1 &mgr;m or less, further, 0.2 &mgr;m or less.
However, there has been known a phenomenon referred to as short channel effect as a factor for hampering miniaturization. The short channel effect gives rise to various problems of lowering of source/drain withstand voltage, lowering of threshold voltage and the like which are caused with a decrease in the channel length (refer to “Submicron Device I”; Mitsumasa Koyanagi et al., pp. 88-138, Maruzen Co., Ltd., 1987).
According to the reference, there has mostly known a punch through phenomenon as one of causes of the decrease in withstand voltage. According to the phenomenon, with a decrease in the channel length, potential influence of a depletion layer on the side of a drain effects on the side of a source and the diffusion potential on the side of the source is lowered (barrier lowering phenomenon induced by drain) by which there is brought about a situation in which control of majority carriers by the gate voltage becomes difficult.
Such a short channel effect poses a problem which must be overcome in carrying out miniaturization. Further, as a representative example of short channel effect, lowering of the threshold voltage is pointed out. This seems to be caused by widening of the depletion layer.
Although various countermeasures have been performed in respect of the short channel effect mentioned above, a countermeasure which is mostly carried out generally is channel dope. The channel dope is a technology for restraining the short channel effect by adding a very small amount of impurity elements such as P (phosphorus) or B (boron) over an entire channel forming region (Japanese Unexamined Patent Publication No. JP-A-4-206971, Japanese Unexamined Patent Publication No. JP-A-4-286339 and so on).
The channel dope is performed with a purpose of controlling the threshold voltage and restraining the punch through phenomenon. However, the channel dope technology is provided with a drawback of imposing serious restriction on the field effect mobility (hereinafter, referred to as mobility) of TFT. That is, movement of carriers is hampered by impurity elements which are added intentionally and the carrier mobility is significantly deteriorated.
SUMMARY OF THE INVENTION
The present invention has been carried out in view of the above-described problems and it is an object of the present invention to provide a semiconductor device having a totally new structure capable of simultaneously realizing high operational function (high mobility) and high reliability (high withstand voltage characteristic) and its fabrication method.
According to an aspect of the present invention, there is provided a semiconductor device including a source region, a drain region and an activation region formed by utilizing a crystalline semiconductor wherein the activation region comprises Si
x
Ge
1−x
(0<x<1) regions formed by locally adding germanium and Si regions where germanium is not added, and a depletion layer widening from the drain region toward the source region is restrained by the Si
x
Ge
1−x
(0<x<1) regions locally provided.
According to another aspect of the present invention, there is provided a semiconductor device including a source region, a drain region and an activation region formed by utilizing a crystalline semiconductor wherein the activation region comprises Si
x
Ge
1−x
(0<x<1) regions formed by locally adding germanium and Si regions where germanium is not added, and a depletion layer widening from the drain region toward the source region is restrained by the Si regions locally provided.
According to another aspect of the present invention, there is provided a semiconductor device including a source region, a drain region and an activation region formed by utilizing a crystalline semiconductor wherein the activation region comprises Si
x
Ge
1−x
(0<x<1) regions formed by locally adding germanium and Si regions where germanium is not added, and a depletion layer widening from the drain region toward the source region is restrained and a threshold value voltage is controlled by the Si
x
Ge
1−x
(0<x<1) regions locally provided.
According to another aspect of the present invention, there is provided a semiconductor device including a source region, a drain region and an activation region formed by utilizing a crystalline semiconductor wherein the activation region comprises Si
x
Ge
1−x
(0<x<1) regions formed by locally adding germanium and Si regions where germanium is not added, and a depletion layer widening from the drain region toward the source region is restrained and a threshold value voltage is controlled by the Si regions locally provided.
The gist of the present invention resides in that two kinds of regions having different band structure are intentionally formed by locally adding germanium to the activation region and the depletion layer widening from the drain side toward the source side is restrained by utilizing a difference between the band structures. Incidentally, the activation region is referred to as a region sandwiched between the source and the drain region (or between LDD regions)
Further, the inventors define a technical term of “pinning” with a meaning of “restraining” since the effect of restraining the depletion layer is achieved as if the depletion layer were pinned. Further, the semiconductor device utilizing the present invention is referred to as “pinning FET” (or pinning TFT) and is clearly differentiated from the conventional semiconductor device.
The semiconductor device according to the present invention comprising the above-described constitution realizes simultaneously high operational function and high reliability. An explanation will be given of details in respect of the semiconductor device according to the present invention by embodiments shown below.
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Crane Sara
Fish & Richardson P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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