Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2000-08-31
2001-12-04
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S052000, C365S210130, C257S390000
Reexamination Certificate
active
06327166
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a layout pattern of a memory cell array region having a memory cell and a peripheral region thereof.
2. Description of the Background Art
A memory cell array structure of a conventional semiconductor device having a DRAM and the like includes a plurality of memory cells arranged in a matrix. One power wiring is inserted and provided in every predetermined number of memory cells. The power wiring is a power wiring for power supply which serves to enhance supply capabilities of a source potential or a ground potential (GND) by relatively increasing a formation width, and is usually formed of metal such as aluminum, copper or the like. The power wiring is formed in a power wiring region which is specially provided for forming only the power wiring.
In the power wiring region, an element such as a transistor is not formed in an area positioned under the power wiring. Therefore, a difference between coarse and fine portions is made on a mask pattern for forming a memory cell between the memory cell array region where a plurality of memory cells are formed and the power wiring region. In the mask pattern for forming a memory cell, a pattern width of the power wiring region where the memory cell is not formed at all becomes much larger than a pattern width of the memory cell array region.
In the case where a resist is subjected to patterning with a mask pattern in which the difference between coarse and fine portions is thus made remarkably after an exposing step using a photomask, there has been the following drawback. More specifically, uneven irradiation is generated by various phenomena such as diffraction interference of light and the like so that a pattern boundary becomes blurred. For this reason, the patterning cannot be performed with high precision. Thus, the patterning controllability of a memory cell is deteriorated.
Moreover, a difference between coarse and fine portions is usually made on the mask pattern for forming a memory cell between the memory cell array region and a peripheral portion thereof (where the memory cell is not formed). Therefore, there has been the drawback that the patterning controllability of the memory cell is deteriorated as described above.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, it is an object of the present invention to provide a semiconductor device having a layout structure in which a memory cell has excellent patterning controllability.
A first aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate, a memory cell array region formed on the semiconductor substrate and having a memory cell provided in an array, and a memory cell array adjacent region provided on the semiconductor substrate adjacently to the memory cell array region and having a dummy cell, wherein a pattern of at least a part of the dummy cell of the memory cell array adjacent region is formed to have a line symmetrical relationship with a pattern of at least a part of the memory cell with respect to a boundary line between the memory cell array region and the memory cell array adjacent region in a vicinal region of the boundary line.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the dummy cell is formed with the same pattern as the memory cell, the same pattern including a normal image and a mirror image.
A third aspect of the present invention is directed to the semiconductor device according to the first or second aspect of the present invention, wherein the dummy cell includes a substrate potential setting portion capable of setting a substrate potential of the semiconductor substrate to a fixed potential.
A fourth aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate, a memory cell array region formed on the semiconductor substrate and having a memory cell provided in an array, and a power wiring region provided on the semiconductor substrate adjacently to the memory cell array region and having a power wiring for power supply provided thereon, wherein the power wiring region includes a dummy cell having a pattern dimension equal to a pattern dimension of the memory cell.
A fifth aspect of the present invention is directed to the semiconductor device according to the fourth aspect of the present invention, wherein a pattern of at least a part of the dummy cell is formed to have a line symmetrical relationship with a pattern of at least a part of the memory cell with respect to a boundary line between the memory cell array region and the power wiring region in a vicinal region of the boundary line.
A sixth aspect of the present invention is directed to the semiconductor device according to the fourth or fifth aspect of the present invention, wherein the dummy cell is formed with the same pattern as the memory cell, the same pattern including a normal image and a mirror image.
A seventh aspect of the present invention is directed to the semiconductor device according to any of the fourth to sixth aspects of the present invention, wherein the dummy cell includes a substrate potential setting portion which is electrically connected to the power wiring and can set a substrate potential of the semiconductor substrate to a potential of the power wiring.
According to the first aspect of the present invention, as described above, the memory cell array adjacent region of the semiconductor device forms the dummy cell having a pattern which is line symmetrical with the pattern of at least a part of the memory cell with respect to the boundary line between the memory cell array region and the memory cell array adjacent region in the vicinal region of the boundary line. Consequently, a difference between coarse and fine portions of the pattern dimension of the mask for forming a memory cell is not made at all in the vicinal region of the boundary line between the memory cell array region and the power region. Therefore, the patterning controllability of the memory cell can be enhanced.
According to the second aspect of the present invention, the dummy cell is formed with the same pattern as the pattern of the memory cell including a normal image and a mirror image. Consequently, a difference between coarse and fine portions of the pattern of the mask for forming a memory cell is not made at all between the memory cell array region and the memory cell array adjacent region. Therefore, the patterning controllability of the memory cell can be enhanced.
According to the third aspect of the present invention, the dummy cell includes the substrate potential setting portion capable of setting the substrate potential of the semiconductor substrate to the fixed potential. Therefore, the substrate potential fixation of the semiconductor substrate can be performed and the stability of a circuit operation can be enhanced.
According to the fourth aspect of the present invention, the power wiring region provided on the semiconductor substrate adjacently to the memory cell array region includes the dummy cell having a pattern dimension equal to a pattern dimension of the memory cell. Therefore, the pattern dimension of the mask for forming a memory cell is identical between the memory cell array region and the power region.
Accordingly, a difference between coarse and fine portions of the pattern of the mask for forming a memory cell is rarely made between the memory cell array region and the power region. Consequently, the patterning controllability of the memory cell can be enhanced.
According to the fifth aspect of the present invention, the semiconductor device forms the dummy cell having a pattern which is line symmetrical with the pattern of at least a part of the memory cell with respect to the boundary line between the memory cell array region and the power wiring region in the vicinal region of the boundary line. Consequen
Itoh Niichi
Morishima Chikayoshi
Nakase Yasunobu
Watanabe Tetsuya
Hoang Huan
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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