Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1997-05-12
2001-12-04
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C438S462000
Reexamination Certificate
active
06326676
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device diced along a scribe line area between a plurality of semiconductor chip areas.
A semiconductor device such as IC or LSI is manufactured using a semiconductor wafer obtained by slicing a semiconductor single crystal ingot as the starting material. More specifically, after forming a plurality of semiconductor chip areas on a semiconductor wafer by effecting various processes for the semiconductor wafer, dicing is effected along the scribe line area formed between semiconductor chip areas to thereby divide into individual semiconductor chips for using them to assemble the semiconductor device.
A dicing blade is used to divide the semiconductor wafer into semiconductor chips. This diamond blade is obtained by causing diamond particles to adhere to a surface, which becomes the cutting portion of a round grindstone having a thickness of scores &mgr;m through such adhesive material as a nickel plating layer, and the diamond particles are pressed against the semiconductor wafer while revolving at as high speeds as ten thousands rpm to cut along the scribe line area. Since heat is generated during the dicing operation, the operation is performed while cooling by pouring water over the semiconductor wafer.
FIG. 5
is a plan view for explaining conventional dicing, and
FIG. 6
is a cross-sectional view taken on line VI—VI in FIG.
5
.
In
FIGS. 5 and 6
, numeral
1
designates a semiconductor wafer;
2
, a semiconductor chip area formed on the semiconductor wafer
1
; and
3
, an insulating protective film consisting of oxide (SiO2) for protecting the surface of each semiconductor chip area
2
and the like, and this insulating protective film
3
is actually formed to have multilayer film structure. Numeral
4
designates a pad electrode consisting of Al and the like formed at a desired position on each semiconductor chip area
2
;
5
, a scribe line area formed between each of the semiconductor chip areas
2
;
6
, a scribe center;
7
, a scribe edge; and
8
, an over-coated film consisting of a nitride film (SiN) covering the pad electrode
4
and the scribe line area
5
, and the like. In this respect, numeral
13
designates a pattern for process monitor called “Scribe TEG (Test Element Group)”, which may be formed and may not be formed.
The dicing is started by positioning a dicing blade in the scribe center
6
of the scribe line area
5
to press it against the semiconductor wafer
1
in
FIGS. 5 and 6
. During the dicing, it is performed in a state in which the semiconductor wafer
1
is fixed by an appropriate supporting jig, and after dicing in one direction (for example, X direction) of the semiconductor wafer
1
is completed, dicing in another direction (for example, Y direction) is performed. After dicing in the X and Y directions is completed, the semiconductor wafer
1
is divided into individual semiconductor chips by releasing the fixed state by the supporting jig. Numeral
16
designates an example of an actual width for cutting using the dicing blade.
In a conventional semiconductor device, when a semiconductor wafer is divided by dicing, there is a problem in which indeterminate rupture, so-called chipping occurs along the edge of the cutting line of the semiconductor wafer in contact with the dicing blade.
This chipping occurs and causes a chipping portion indicated by numeral
9
in FIG.
5
. When the chipping portion
9
enters the semiconductor chip area
2
from the scribe line area
5
, there is a possibility that the semiconductor chip divided by dicing does not properly operate, becoming a defective element in the worst case.
To this end, there has been conceived a counter measure to prevent chipping from occurring by removing the over-coated film in the scribe line area to directly dice the surface of the semiconductor wafer. According to this proposal, however, since the scribe line area is exposed, when wire bonding is effected for the semiconductor chip after completion of the dicing, there is a drawback that the wire comes into contact with a part of the scribe line area to cause a short-circuit, etc.
Also, recently, there has been generally arranged a pattern
13
for process monitor called a “Scribe TEG (Test Element Group)” within the scribe line area for the purpose of shrinking the chip, but since this TEG is formed by stacking an insulating film and a conductive film, it causes the dicing blade to be clogged during dicing, and further causes chipping to easily occur. To avoid this, it is good enough to enlarge the width of the scribe line area, but in this case, it is not desirable because this runs counter to the chip shrinkage.
SUMMARY OF THE INVENTION
The present invention has been achieved to solve such problems, and its object is to prevent chipping from entering the semiconductor chip area when the semiconductor wafer is diced along the scribe line area provided between each of the semiconductor chip areas.
A semiconductor device according to the present invention is characterized in that a portion of the scribe line area on the side of the semiconductor chip area has been provided with a chipping preventing portion.
According to a semiconductor device of the present invention, the chipping preventingportion has been provided in the scribe line area formed between a plurality of semiconductor chip areas on a semiconductor wafer, and therefore, it is possible to prevent the entry of chipping into the semiconductor chip area, by the chipping preventing portion, which is likely to occur when dicing the semiconductor wafer along the scribe line area provided between each of the semiconductor chip areas.
REFERENCES:
patent: 4610079 (1986-09-01), Abe et al.
patent: 5136354 (1992-08-01), Morita et al.
patent: 5530280 (1996-06-01), White
patent: 5763936 (1998-06-01), Yamaha et al.
patent: 5834829 (1998-11-01), Dinkel et al.
patent: 6077315 (1994-03-01), None
Asami Yukio
Kobayashi Hirotaka
Ohde Tomoshi
Prenty Mark V.
Sonnenschein Nath & Rosenthal
Sony Corporation
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2560680