Semiconductor device

Details Semiconductor device Semiconductor device

1999-04-12

2001-02-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

C365S230030

Reexamination Certificate

active

06195306

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to power supply circuits of a semiconductor memory and, more specifically, to a control method for achieving low power dissipation.
In this specification, reference will be made to the following publications: Japanese Patent Laid-Open No. 105682/1995 (called the Cited Reference 1; corresponding to U.S. Pat. No. 5,463,588), and Japanese Patent Laid-Open No. 161481/1997 (called the Cited Reference 2).
Semiconductor memories extensively utilize what is known as an on-chip voltage limiter method (i.e., power-down method) whereby the semiconductor chip lowers an externally supplied voltage to generate an internal voltage for use as a power supply. The method is used to reduce power dissipation of circuits or to improve reliability of fine elements in the device. In achieving such objects, voltage limiter circuits (power-down circuits) are utilized to generate the internal supply voltage.
A voltage limiter circuit consumes a steady current so as to maintain an output voltage level even when the semiconductor memory is in standby mode. As a way to reduce power dissipation in the standby state, the Cited Reference 1 proposes a total of eight voltage limiter circuits, i.e., two limiter circuits furnished to each of four memory cell arrays; and a single, common voltage limiter circuit that is common to all memory cell arrays (
FIG. 3
in the Cited Reference 1). The common voltage limiter circuit is constantly in operation. The eight voltage limiter circuits start operating simultaneously when the memory is accessed, and four of the circuits are allowed to remain active upon elapse of a predetermined period of time following the start of the access.
The Cited Reference 2 discloses first and second voltage limiters furnished corresponding to respective first and second banks, along with a description of operation timings of the limiters. When the first bank is ordered to be activated, the first voltage limiter generates an internal voltage. If the second bank is ordered to be activated while the first bank is still active, the secondvoltage limiter also generates an internal voltage in cooperation with the first voltage limiter (
FIG. 12
of the Cited Reference 2).
SUMMARY OF THE INVENTION
The inventors of the present invention have studied the power dissipation of SDRAMs (synchronous dynamic random access memories) in active standby mode. The active standby mode of the SDRAM is a mode in which a memory bank is left active to retain one-word data in sense amplifiers in preparation for memory access, with a read or a write command yet to be issued. Whereas it takes a relatively long time to read data from dynamic memory cells, the data, once placed in sense amplifiers, may be read at high speed because the data thus retained are handled as if they were in a column of an SRAM (static random access memory).
Active standby mode is entered when a bank active command is applied. The application of the bank active command selects a word line and operates sense amplifiers, thus causing a large current to flow. Then with no further command issued, no power dissipation should occur in theory. In practice, where a voltage limiter circuit is included, a current flows to that circuit. If both standby and operating voltage limiter circuits operate, they dissipate a fairly large current (generally of several to tens of mA). In particular, many synchronous DRAMs are arranged to leave their banks active to take advantage of the high-speed data transmission feature. This means that an active standby current can have a significant effect on the power dissipation of the system as a whole.
In the disclosure of the Cited Reference 1, bank-related operations specific to SDRAMs are not considered. No technique is disclosed in connection with controlling the driving capability of voltage limiters in units of a plurality of memory arrays, memory blocks or banks. The inventors of this invention found that if the techniques of the Cited Reference 1 were applied to SDRAMs, as many as eight voltage limiter circuits (nine if a common voltage limiter circuit is included) would operate simultaneously in the initial stage of an active period, causing an excessively large operation current to flow at peak time. With the initial stage ended and with the active period still in effect, four voltage limiter circuits (five if the common voltage limiter circuit is included) would be in operation. This, the inventors found, will give rise to an unnecessarily high level of power dissipation during the active period.
The Cited Reference 2 does not take the active standby mode of SDRAMs into consideration. The inventors of this invention found that successively activating a plurality of memory banks in the SDRAM would cause a growing number of the corresponding voltage limiter circuits to become active; and putting a plurality of memory banks in active standby mode would unnecessarily add up operation currents of the corresponding limiter circuits. The increase of such operation currents can become a serious problem if a large number of banks are involved.
It is therefore an object of the present invention to overcome the above-described drawbacks and disadvantages and to provide a semiconductor device comprising: first and second memory banks activated by first and second commands (first and second control signals) respectively; a power supply line for supplying a predetermined voltage to the first and the second memory banks; and first and second power supply circuits (first and second voltage generating circuits) having respective output nodes connected to the power supply line, the first and the second power supply circuits generating the predetermined voltage; wherein the first power supply circuit starts generating the predetermined voltage in response to the first command; and wherein, upon input of the second command with the first memory bank left active, the first power supply circuit stops generating the predetermined voltage in response to the second command while the second power supply circuit starts generating the predetermined voltage in response to the second command.
Other objects, features and advantages of the invention will become more apparent upon a reading of the following description taken with reference to the appended drawings.


REFERENCES:
patent: 5463588 (1995-10-01), Chonan
patent: 5659519 (1997-08-01), Lee et al.
patent: 5781494 (1998-07-01), Bae et al.
patent: 9-161481 (1997-06-01), None

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