Semiconductor device

Details Semiconductor device Semiconductor device

1999-01-04

2001-05-08

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S163000

Reexamination Certificate

active

06229363

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device equipped with a clock phase adjusting circuit, such as a DLL (Delay Locked Loop) circuit, for generating an internal clock signal delayed by a predetermined phase, by adjusting the phase of an external clock signal supplied from outside. More particularly, this invention relates to a semiconductor device having the function of assuredly storing data in a predetermined correct phase with respect to an external clock signal, and outputting the data irrespective of variance of device characteristics and changes of an ambient temperature, a power source voltage, etc., by generating an internal clock signal delayed by a predetermined cycle, such as one cycle, from the external clock signal and synchronizing the phase of the data inputted to a dynamic random access memory (hereinafter called the “DRAM”), etc., with the phase of the internal clock signal.
2. Description of the Related Art
To begin with, a construction of a semiconductor device equipped with the clock phase adjusting circuit according to the prior art, and its operation, will be explained with reference to
FIGS. 1
to
3
that will be mentioned later in “BRIEF DESCRIPTION OF THE DRAWINGS” in order to make the problems, which are encountered when clock phase adjustment is carried out by conventional techniques, more easily understood.
Recent CPUs (Central Processing Units) operate in synchronism with a high-speed external clock signal of 100 MHz or more than 100 MHz. In other words, the ability of the CPUs for processing data has become extremely high. In contrast, the operation speed of general-purpose DRAMs is so low that these DRAMs have difficulty in inputting and outputting the data required by the CPUS. To cope with this situation, various novel DRAMs, such as synchronous DRAMs (generally abbreviated to the “SDRAMs”) which are operating in synchronism with a high-speed external clock signal of 100 MHz or more than 100 MHz, and which are capable of inputting and outputting the data required by the CPUs, have been proposed.
When the data input/output operation is executed, however, a data indeterminate period occurs due to a change of an ambient temperature, a fluctuation of a power source voltage, and so forth. Therefore, a data determinate period (data window) is the value obtained by subtracting the data indeterminate period from tCLK (time corresponding to one cycle of the external clock signal). In this case, as the external clock signal becomes more high-speed, tCLK becomes shorter and the setting of the timing of the data input/output operation becomes more difficult. Conversely, an increase of the data indeterminate period resulting from the changes of the ambient temperature and the power source voltage must be minimized, in order to execute without error the data input/output operation under a relatively high-speed external clock signal.
To minimize the increase of such a data indeterminate period, a clock phase adjusting circuit, such as a DLL, capable of securing a data window having a sufficiently wide period even with a relatively high-speed external clock signal, becomes effective.
In
FIG. 1
, a block circuit diagram showing the construction of a semiconductor device having an ordinary clock phase adjusting circuit, is illustrated. The clock phase adjusting circuit in the semiconductor device shown in
FIG. 1
, such as a digital DLL circuit
100
, includes a delay circuit
450
comprising a plurality of delay lines
400
and dummy delay lines
440
for generating an internal clock signal INCLK delayed by a predetermined phase, by changing a delay time (i.e., delay amount) of an external clock signal EXCLK inputted from the outside through an input buffer
800
; a phase comparing circuit
660
for comparing the phase of the signals obtained by dividing a frequency of the external clock signal EXCLK with the phase of the signal inputted from the dummy delay line
440
through a dummy output buffer
990
and a dummy input buffer
880
; and a delay control circuit
550
for selecting the delay time of the delay line
400
and the dummy delay line
440
, on the basis of a phase comparison result by this phase comparing circuit
660
.
The explanation will be given in further detail. The external clock signal EXCLK is amplified to a predetermined level by the input buffer
800
and after the frequency of the amplified external clock signal is divided by a division circuit
300
, this clock signal is supplied to the delay circuit
450
and is also supplied as a first input signal to the phase comparing circuit
660
.
In this case, the dummy input buffer
880
is disposed in order to compensate for the phase delay of the external clock signal CLK due to the input buffer
800
on the input side of the phase comparing circuit
660
. Further, the dummy output buffer
990
is disposed so as to compensate for the phase delay of the internal clock signal due to the output buffer
900
which outputs the data DATA in synchronism with the internal clock signal INCLK generated by the delay line
400
. Therefore, the external clock signal EXCLK inputted to the dummy delay line
440
through the division circuit
300
is supplied as the second input signal to the phase comparing circuit
660
, through the dummy output buffer
990
and the dummy input buffer
880
.
This phase comparing circuit
660
compares the phase of the first input signal with that of the second input signal, and inputs a result of the phase comparison of these two input signals to the delay control circuit
550
. This delay control circuit
550
selects and adjusts the delay time of the delay line
400
and the dummy delay line
440
so that the phase difference between the external clock signal EXCLK and the internal clock signal INCLK attains predetermined cycle or cycles (i.e., at least one clock cycle), such as one cycle (360 degrees). As a result, the external clock signal EXCLK inputted to the delay line
400
is provided with the delay time adjusted by the delay control circuit
550
and is then supplied to the output buffer
900
. This output buffer
900
outputs the data DATA to the outside of the semiconductor device in synchronism with the internal clock signal INCLK supplied from the delay line
400
(DOUT).
When an operation frequency of the SDRAM is relatively low, the digital DLL circuit having the ordinary construction described above can fully exert the function of adjusting the phase of the external clock signal. In other words, the digital DLL circuit generates the internal output clock signal INCLK whose phase is in synchronism with the external clock signal on the basis of this external clock signal EXCLK, eliminates an influence of the delay resulting from wiring for transmitting the clock signal, etc., inside the SDRAM and can output the data outside the SDRAM in synchronism with the external input clock signal. However, the digital DLL circuit mounted to an DRAM having a high operation speed of 100 MHz or more than 100 MHz must be able to execute the delay control with extremely high accuracy.
The digital DLL circuit includes a delay line formed by connecting, in series with each other, a plurality of unit delay elements each comprising the combination of a plurality of logic gates such as NAND gates and inverters. Generally, the delay time (i.e., delay amount) of the unit delay element is about 200 psec (200×10
−12
sec) at minimum. To cope with a relatively high operation speed exceeding 100 MHz, however, a high accuracy digital DLL circuit capable of controlling the delay time of not larger than 200 psec becomes necessary. The accuracy of the delay time control can be improved, in principle, by using a unit delay device having the delay time of not larger than 200 psec. However, in order to secure the delay time of a certain accuracy only by using the unit delay elements having the delay time of not larger than 200 psec, a large number of unit delay devices are necessary, and the circuit construction for co

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