Semiconductor device

Details Semiconductor device Semiconductor device

2000-01-10

2001-10-23

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Schottky barrier

C257S473000, C438S571000

Reexamination Certificate

active

06307245

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a gate embedding layer on the surface of a semiconductor substrate reducing the effective gate length and reducing the drain conductance (g
ad
), and a method of producing the same.
2. Description of the Related Art
It is necessary to decrease the capacitance between a gate and a source in order to improve the high-frequency characteristics of a semiconductor device, particularly to achieve a high gain, and one of effective means for this purpose is to reduce the gate length. For this reason, a semiconductor device disclosed in Japanese Laid-Open Patent Publication No.5-218100 using a T-shaped gate electrode has been suggested. However, reducing the gate length leads to an increase in the drain conductance, that in a high-output power device, in particular, may lower the efficiency. Accordingly, the conventional T-shaped gate electrode has been insufficient to reduce the drain conductance.
With this background, semiconductor devices comprising a gate electrode that has a gate embedding layer and extending portions have been studied.
FIG. 6
is a longitudinal sectional view of a semiconductor device showing an example. Reference numeral
30
denotes a semiconductor substrate that consists of a semi-insulating GaAs substrate
31
, an n-GaAs active layer
32
, a gate embedding layer
33
comprising an n-GaAs layer and a n
+
-GaAs layer
34
. Numeral
37
denotes a drain electrode made of an AuGe-based metal,
38
denotes a source electrode made of an AuGe-based metal,
40
denotes a gate electrode made of an Al-based metal,
40
a
denotes an embedded portion of the source electrode
40
, and
40
b
,
40
c
denote extending portions of the gate electrode
40
that is joined with the gate embedding layer
33
. The extending portions
40
b
,
40
c
extend laterally outwardly in opposite directions.
As shown in
FIG. 6
, it is made possible to reduce the effective gate length by embedding a central portion of the bottom of the gate electrode in the gate embedding layer
33
and reducing the width of the embedded portion
40
a
that is nearest to a channel. Also because the extending portions
40
b
,
40
c
on both sides (drain electrode and source electrode) of the embedded portion
40
a
are joined with the gate embedding layer
33
, drain conductance can be reduced particularly when the value of drain voltage (VD) is increased, compared to a structure without extending portions on both sides.
FIGS. 7A-7D
show a schematic flow sheet showing a conventional method of producing the semiconductor device shown in FIG.
6
. As shown in
FIG. 7A
, a dummy gate electrode
35
made of photoresist applied to form the embedded portion
40
a
is formed on the n
+
-GaAs layer
34
in first photolithography step. This is followed by the deposition of an insulation layer
36
made of SiO
2
of a predetermined thickness, on the dummy gate electrode
35
and the n
+
-GaAs layer
34
, as shown in FIG.
7
B. Then as shown in
FIG. 7C
, the n
+
-GaAs layer
34
is etched through till the gate embedding layer
33
is exposed, thereby to form an opening in the n
+
-GaAs layer
34
. Formed thereafter are the drain electrode
37
, the source electrode
38
, and photoresist
39
applied to form the extending portions
40
b
,
40
c
in second photolithography step. Then as shown in
FIG. 7D
, etching is done so as to penetrate through the gate embedding layer
33
and increase the width of the opening. Thus a metal layer to form the gate electrode is deposited, and the gate electrode
40
having the embedded portion
40
a
and the extending portions
40
b
,
40
c
is formed, as shown in FIG.
7
E.
In the conventional method, however, the embedded portion
40
a
and the extending portions
40
b
,
40
c
of the gate electrode
40
are formed in separate photolithography steps, and therefore misalignment during the photolithography step causes the extending portions
40
b
,
40
c
to be formed unsymmetrically with respect to the embedded portion
40
a.
In a high output power device, as it ordinarily employs a multi-finger pattern for power output, in case the extending portions
40
b
,
40
c
are formed unsymmetrically with respect to the embedded portion
40
a
, there has been such a problem that fingers that are offset toward the drain electrode and fingers that are offset toward the source electrode are formed alternately, thus making causes for uneven operation or lower performance.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a method of producing a semiconductor device where the extending portion of the gate electrode will never be formed at a position shifted toward the drain electrode or the source electrode, and a high-performance semiconductor device obtained by the method.
To solve the above problems, the method of producing a semiconductor device comprising a semiconductor substrate that has a gate embedding layer, a gate electrode, a source electrode and a drain electrode that are disposed to interpose the gate electrode according to the present invention comprises the steps of: (a) forming a first insulation layer of a predetermined thickness on the surface of the gate embedding layer; (b) etching through the first insulation layer to form a first opening through which the gate embedding layer is exposed; (c) forming a second insulation layer on the top surface of the semiconductor substrate that includes the first opening; (d) etching the second insulation layer to expose the central portion of the gate embedding layer in the first opening and forming a pair of side walls having a predetermined width of the second insulation layer on the inner surface of the first opening; (e) forming a second opening having width smaller than that of the first opening in the gate embedding layer below the first opening by etching with the pair of side walls and the first insulation layer being used as masks; (f) removing at least one of the pair of side walls thereby to form a step that includes the top surface of the gate embedding layer around the second opening; (g) depositing a he gate electrode forming metal layer in the first opening and the second opening; (h) removing the first insulation layer to form a gate electrode; and (i) forming the drain electrode and the source electrode, wherein the gate electrode has an embedded portion embedded in the gate embedding layer, two first extending portions joined with the step surface and two second extending portions formed on the associated first insulating layers so that lower surfaces of the two second extending portions are located at a level, above the step surfaces, equal to a height of the first insulating layers.
According to the present invention, as the pair of side walls having the predetermined width comprising insulation layers are formed on the inner surface of the first opening and the gate embedding layer is formed by using the pair of side walls and the first insulation layer as the masks, the second opening that becomes the embedded portion is formed while being separated from both inner surfaces of the first opening inward by the widths of the side walls. As a consequence, the embedded portion and the first extending portion are formed in a self-aligning way in accordance to the positions and widths of the second opening and the first opening, so as the first extending portions not to be formed unsymmetrically with respect to the embedded portion.
It is preferable to remove one, located on the drain electrode side, of the pair of side walls in the step of forming the step surface, and to remove the other side wall remaining on the source electrode side in the step of forming the gate electrode, thereby to form the first extending portion on the drain electrode side. Thus, the source resistance can be reduced because there is not the first extending portion on the source electrode side.
It is also preferable to provide a step of forming a third insulation layer over t

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