Semiconductor device

Details Semiconductor device Semiconductor device

1999-02-26

2001-01-02

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C257S138000, C257S139000, C257S144000

Utility Patent

active

06169299

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bipolar type semiconductor device having a MOS gate and, more specifically, to a semiconductor device suitable for use in a thyristor.
2. Related Art
A MOS thyristor, i.e. a combination of a MOSFET with a thyristor structure, is a transistor within which a MOS gate acts to supply electrons from a cathode to a floating emitter region as well as to provide holes from an anode to a base region, thereby performing a thyristor action within the transistor.
FIG. 11
shows an example of a conventional MOS thyristor. The MOS thyristor comprises a p
+
type emitter layer
10
, an n
+
type buffer layer
12
, an n
−
type base region
14
, a p
−
type base region
16
, a floating emitter region
22
, and N
+
type impurity diffusion layers
18
a
and
18
b.
Furthermore, a gate electrode
40
is formed on the surfaces of the p
−
type base region
16
and the n
+
type impurity diffusion layer
18
b
that functions as a source region via a gate insulation layer
42
. The operation of a thyristor is regulated by driving a MOS gate with the gate electrode
40
. Namely, the n
+
type impurity diffusion layer
18
b
(i.e. the source region), the p
−
type base region
16
, the n
−
type base region
14
, the n
+
type buffer layer
12
, and the p
+
type emitter layer
10
constitute an insulated-gate bipolar transistor (hereinafter abbreviated as “IGBT”) for a thyristor action.
When a thyristor is activated in the MOS thyristor described above, electron injection occurs from the n
+
type floating emitter region
22
into the p
−
type base region
16
and at the same time holes are provided from the p
+
type emitter layer
10
through the n
−
type base region
14
into the p
−
type base region
16
. However, in a transistor having such a structure, the regulating function of the MOS gate is lost and the turn-off operation on the thyristor becomes unavailable when a latch-up phenomenon occurs due to a high injection condition in a parasitic thyristor consisting of the n
+
type emitter region
18
a,
p
−
type base region
16
, n
−
type base region
14
, n
+
type buffer layer
12
, and p
+
type emitter layer
10
. For this reason, an attempt is made to raise the doping level of a p
−
type base region
16
directly underneath a cathode electrode
50
or to increase its diffusion depth so that latch-up of the parasitic thyristor is prevented. However, increasing the doping level of the p
−
type base region directly underneath the cathode electrode in order to sufficiently prevent latch-up of the parasitic thyristor results in a more complicated fabrication process. Also, increasing the diffusion depth leads to an increase in the unit cell size, making the safe operating area narrower and the ON-state voltage higher as well.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a bipolar type semiconductor device containing a MOS gate, which allows a further reduction of the ON-state voltage as well as a reliable turn-off action as enabled by suppressing the operation of a parasitic thyristor.
The semiconductor device of the present invention comprises:
a first semiconductor layer of a first conductive type;
a second semiconductor layer of a second conductive type formed on one side of the principal planes of the first semiconductor layer;
a third semiconductor layer of the first conductive type selectively formed on the surface of the second semiconductor layer;
a fourth semiconductor layer of the second conductive type selectively formed on the surface of the third semiconductor layer;
a fifth semiconductor layer of the second conductive type selectively formed on the surface of the third semiconductor layer apart from the fourth semiconductor layer;
a sixth semiconductor layer of the first conductive type located between the fourth semiconductor layer and the fifth semiconductor layer, which can form a channel region;
a gate electrode formed via an interposed gate insulation layer on the surface of at least the sixth semiconductor layer;
an insulation layer located within the third semiconductor layer and formed either at or near the extremities of at least the fourth semiconductor layer as well as the sixth semiconductor layer on the sides facing the first semiconductor layer;
a first main electrode formed on the surfaces of the third semiconductor layer and the fourth semiconductor layer; and
a second main electrode formed on the other side of the principal planes of the first semiconductor layer,
wherein the fifth semiconductor layer has an extended semiconductor portion extending in the direction parallel to the principal plane of the first semiconductor layer.
In the above semiconductor device, a MOS transistor is formed by the fourth semiconductor layer functioning as a source region, the sixth semiconductor layer which can form a channel region, and the fifth semiconductor layer which functions as a drain region as well as a floating emitter region. At the same time, a thyristor is formed by the first, second, third, and fifth semiconductor layers.
In this semiconductor device, the latch-up action of the parasitic thyristor, which exists directly underneath the first main electrode functioning as a cathode electrode, can be prevented by forming an insulation layer at or near the extremities of the fourth semiconductor layer, which functions either as a source region or an emitter region, and the sixth semiconductor layer which can form a channel region.
In other words, by forming the insulation layer at the lower-ends of the fourth semiconductor layer, which functions either as a source region or an emitter region, and the sixth semiconductor layer which can form a channel region, preferably in a manner whereby it traverses the operating regions (i.e. in the direction parallel to the principal plane of the first semiconductor layer), the operation of the parasitic thyristor formed underneath the first main electrode can be suppressed even under a high injection condition wherein a voltage is applied to the second main electrode which functions as an anode electrode, since the fourth semiconductor layer and the sixth semiconductor layer are electrically isolated from the second semiconductor layer by the above insulation layer. Consequently, the semiconductor device of the present invention can perform the turn-on and turn-off operations more reliably than transistors based on conventional configurations.
In addition to these effects, since a portion (extended semiconductor portion) of the fifth semiconductor layer which functions as a floating emitter region is formed in such a manner it stretches in the direction parallel to the principal plane of the first semiconductor layer at the backside (i.e. on the side facing the first semiconductor layer) of the insulation layer, the path for carrier injection from the floating emitter region can be broadened, thereby facilitating the electric current and enabling a reduction of the ON-state voltage.
For the semiconductor device of the present invention, it is preferable to form a high resistance region in the fifth semiconductor layer and in contact with the sixth semiconductor layer. Such a high resistance region formed in a portion of the fifth semiconductor layer which functions as a floating emitter region ensures a reliable turn-off operation. This is because the electric field applied to the pn junction comprising the channel region (i.e. the sixth semiconductor layer) of the first conductive type and the floating emitter region (i.e. the fifth semiconductor layer) of the second conductive type can be relieved by the high resistance region when a thyristor containing a MOS gate is being turned-off. Thus, the pn junction comprising the channel region and the floating emitter region is not subjected to a breakdown current, enabling a reliable turn-off operation for the transis

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