Semiconductor device

Details Semiconductor device Semiconductor device

1999-11-04

2001-01-30

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S230080, C365S189050, C365S190000

Reexamination Certificate

active

06181633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device using a dynamic RAM (hereinafter, referred to as “DRAM”). In particular, the present invention relates to a technique that is characterized by means for easily setting an optimal page length and data input/output width in accordance with a system to which the DRAM is applied and is effective for achieving low power consumption and high speed for the DRAM.
2. Description of the Prior Art
In recent years, DRAMs are utilized in the form of a macrocell so as to be mounted on one semiconductor substrate together with a microprocessor or an ASIC (application specific IC, hereinafter referred to as “logic”).
When the DRAM is mounted on a semiconductor substrate together with a microprocessor or a logic, the constraints caused by the number of pins of the DRAM can be eliminated, unlike the case where the DRAM is attached externally. Therefore, the data width for data input and output can be extended, and the data transfer rate between the DRAM and the logic can increase significantly. In addition, the DRAM and the logic can be connected over a short distance by metal wiring, so that the parasitic capacitance of input/output wiring can decrease significantly. Thus, low power consumption can be achieved.
The basic operation of the DRAM includes the first operation period, the second operation period, and the third operation period. In the first operation (hereinafter, referred to as “RAS cycle”), the data of memory cells in a specified area is read by activating a sense amplifier and is stored. In the second operation (hereinafter, referred to as “CAS cycle”), the data stored in the sense amplifier is divided by a predetermined unit, and is output to the outside sequentially, or the data input from the outside is written in the sense amplifier. In the third operation (hereinafter, referred to as “precharge cycle”), a precharge state is set for a next operation cycle.
As an independent DRAM product for practical use, DRAMs of various specifications such as a fast page mode DRAM, an EDO DRAM, and a synchronous DRAM are used commonly. All of these DRAMs are configured based on the basic operations described above, and also a DRAM macrocell mounted with other components on a semiconductor substrate is configured based on any one of these specifications.
Furthermore, in the DRAM macrocell mounted with other components, the storage capacity or the data width for input and output is changed in accordance with the specification of the semiconductor device to which the DRAM macrocell is applied and the product use for each predetermined unit.
The semiconductor devices provided with the DRAMs are used in various fields, and the performance required for the DRAM is varied with the use. For example, in the case where the DRAM is used in a system that processes image data for graphics, a high speed clock of 100 MHz or more is required to increase the data transfer rate. For this reason, wide page length and high speed in the data transfer rate are required in a page mode or a mode comparable thereto.
Furthermore, in the case where the DRAM is used in a system of portable equipment or consumer products, the DRAM is used generally in a random access mode using a clock frequency of about several tens MHz or an access mode using a relatively short page length. Thus, low power consumption is required rather than the high speed data transfer rate.
The page operation of the DRAM is an operation to read (or write) the data in the sense amplifier activated in the first operation period for each predetermined unit sequentially in the second operation period. Therefore, the page length can be larger as the activated area is larger. On the other hand, the power consumption of the DRAM depends significantly on the area of the activated memory cells and the number of the activated sense amplifiers, so that the power consumption can be smaller as the activated area is smaller.
In the conventional semiconductor device using the DRAM, the area of the memory cells and the number of the sense amplifiers to be activated in the first operation period are fixed. Moreover, since the DRAM is supposed to be mounted in semiconductor devices for various uses, the page length is as relatively long as that of an independent DRAM product, in order to avoid constraints in the functions. Therefore, the DRAM has extra functions that are not required for portable equipment or consumer products, which place importance on low power consumption, and the low power consumption is not sufficiently achieved.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor device including means for easily setting an optimal page length in accordance with the application use of the DRAM macrocell so that the low power consumption can be achieved.
A semiconductor device of the present invention includes memory cells, each of which is a dynamic storage device; a memory cell array where the memory cells in a predetermined number are arranged in a matrix, the memory cells being connected to intersections of orthogonal word lines and bit lines; first sense amplifying circuits for amplifying electric potentials of the bit lines; main bit lines arranged in parallel to the bit lines; a memory block array formed such that a plurality of memory blocks including switching circuits share the main bit lines, the switching circuits controlling conductivity between outputs of the first sense amplifying circuits and the main bit lines; first selecting means for selecting the word lines and the first sense amplifying circuits belonging to at least one memory block of the plurality of memory blocks; second selecting means for selecting the switching circuits belonging to one memory block of the plurality of memory blocks; a control signal generating circuit for controlling the second selecting means. The semiconductor device includes a program circuit for selecting either one of acquiring addresses that specify positions of the memory cells as addresses for rows at a first timing and acquiring addresses that specify positions of the memory cells as addresses for columns at a second timing that is different from the first timing.
This embodiment allows the page length to be set arbitrarily and the activated area of the DRAM macrocell to be physically obtained continuously. Therefore, the data transfer rate can be increased. This effect is expected to be significant, especially in a memory interleaving system.
Furthermore, in the semiconductor device of the present invention, preferably, the program circuit selects either one of acquiring at least one address signal for controlling the second selecting means at the same timing as that of an address signal for controlling the first selecting means and acquiring at least one address signal for controlling the second selecting means at a timing that is later than the timing of an address signal for controlling the first selecting means. This embodiment allows the page length to be set arbitrarily and the activated area of the DRAM macrocell to be physically obtained continuously. Therefore, the data transfer rate can be increased. This effect is expected to be significant, especially in a memory interleaving system. It is sufficient to make this selection for at least one address signal, and it is not necessary for all the address signals.
Furthermore, in the semiconductor device of the present invention, preferably, the program circuit selects either one of (a) making ineffective at least one address signal for controlling the first selecting means and connecting the ineffective address signal as an address signal for controlling the second selecting means and (b) treating all address signals for controlling the first selecting means as effective and connecting all the address signals. This embodiment allows the page length to be set arbitrarily and only a minimum activated area to be read or written when the data width is not sufficient

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