Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-10-04
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189070, C365S189011
Reexamination Certificate
active
06219300
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array and especially to improvements for suppressing power consumption or the wearing out of memory cells.
2. Description of the Background Art
FIG. 24
is a block diagram schematically showing a configuration of a conventional semiconductor device with a semiconductor memory. This conventional device
150
comprises a memory cell array
91
, a readout circuit
93
, a word line decoder
97
, and a bit line selector
98
. The memory cell array
91
is provided with a plurality of memory cells (not shown) each connected to one of word lines W and one of bit lines B.
When reading out data held in memory cells, the device
150
operates as follows: First, an address signal A is entered which specifies one memory cell to be read among the plurality of memory cells. Then, the word line decoder
97
selects and drives one of the plurality of word lines W which is connected to the specified memory cell.
As a result, holding signals of a plurality of memory cells which are connected to the driven word line are output to the bit selector
98
through a plurality of bit lines B. The bit line selector
98
selects one of the plurality of bit lines B which is connected to the specified memory cell and transmits the holding signal obtained through that bit line to the readout circuit
93
. The readout circuit
93
determines whether the input holding signal is high or low in level, and outputs that level of signal to a data line D in synchronization with an enable signal E. In this fashion, data is read out from the selected specific memory cell.
For an MCU (microcontroller or microcomputer) in which a CPU and peripheral circuits including a semiconductor memory are incorporated into a single semiconductor chip, in recent years, further speedups have been required and in consideration of environment, there has been the growing need for still further reduction in power consumption. As to speed, it is generally assumed that the operating speed of the readout circuit in the semiconductor memory determines the speed of the entire MCU. As to power consumption, power consumption in the semiconductor memory occupies a large portion of power consumption in the entire MCU.
Speedups and low power consumption are, however, technically conflicting demands, so that it is not easy to achieve both of them. Therefore, it became customary for the MCU users, who make products employing MCUs, to use the MCU with high operating speed and the MCU with low power consumption properly according to their purposes. But some products of the users could be used for such applications that an operating period where speed is paramount and an operating period where low power consumption takes precedence over speed were mixed. Even in such applications, an MCP capable of high-speed operation needs to be used. This results in unnecessary power consumption.
In order to minimize power consumption while using the MCU with high operating speed in such applications, when low power consumption is a high priority, such steps have been taken as to suppress unnecessary operation of the MCU by utilizing an operation-stop or wait mode of the CPU in the MCU or as to keep down the frequency of a clock signal (i.e., internal clock signal), to which the CPU is synchronized, by varying the divisional ratio of an external clock signal fed from the outside to the MCU.
However, the MCU capable of high-speed operation employs, as its readout circuit, a current-driven current mirror circuit with high power consumption. In this circuit, a large current flows in a steady state, so that a slowdown of the operating speed with a low-speed internal clock would make little difference in power consumption. Thus, there has been a problem of incapability in effectively reducing power consumption in the MCU.
The above description illustrates the MCU by way of example, but not only in the MCUs but also in general semiconductor devices with the semiconductor memory, it has been required that the readout circuit should have flexibility and adaptability to the request for high speed or low power consumption according to applications of the device and operating periods.
Further, a nonvolatile semiconductor memory has a problem that the wearing out of memory cells for holding data becomes faster as the operating speed of a write circuit, which forms a pair with the readout circuit, is unnecessarily increased. Therefore, it has also been desired that the write circuit should have flexibility and adaptability to the request for high speed or protection of memory cells according to applications of the device and operating periods.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device comprising: a memory cell array including a plurality of memory cells; a first readout circuit for reading and outputting a signal which is held in a specified memory cell among the plurality of memory cells; and a second readout circuit for reading and outputting a signal which is held in a specified memory cell among the plurality of memory cells, the second readout circuit having a lower operating speed than the first readout circuit, the first and second readout circuits operating exclusively.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a CPU having access to the memory cell array, the CPU including a register, wherein the first and second readout circuits operate exclusively on the basis of a signal held in the register.
According to a third aspect of the present invention, the semiconductor device of the first aspect further comprises: a CPU operating in synchronization with a clock signal and having access to the memory cell array; a frequency divider for dividing an external clock signal fed from the outside by a plurality of ratios to generate signals having a plurality of periods, and selectively supplying one of the signals to the CPU as the clock signal; and a comparator for comparing a divisional ratio of the clock signal to the external clock signal with a reference value, wherein if the divisional ratio is not smaller than the reference value according to a comparison result of the comparator, the second readout circuit exclusively operates among the first and second readout circuits, and if the divisional ratio is smaller than the reference value, the first readout circuit exclusively operates.
According to a fourth aspect of the present invention, the semiconductor device of the third aspect further comprises: an external terminal, wherein the comparator sets a value indicated by a signal fed from the external terminal as the reference value.
According to a fifth aspect of the present invention, the semiconductor device of the first aspect further comprises: a CPU operating in synchronization with a clock signal and having access to the memory cell array; a reference delay generating circuit generating a pulse representing a predetermined delay time of the clock signal from the start of one clock period, for each of the one clock period; and a judging circuit for determining whether a time when the CPU directs the start of the operation of the first or second readout circuit is within the delay time or not, wherein if the time is within the delay time according to a judgment result of the judging circuit, the first readout circuit exclusively operates among the first and second readout circuits, and if the time is not within the delay time, the second readout circuit exclusively operates.
According to a sixth aspect of the present invention, in the semiconductor device of either of the first through fifth aspects, memory cells to be read by the first and second readout circuit are the same.
A seventh aspect of the present invention is directed to a semiconductor device comprising: a memory cell array including a plurality of memory cells; a first write circuit for writing a data signal to a specified memory cell
Burns Doane , Swecker, Mathis LLP
Lam David
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2525716