Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1998-07-27
2001-03-06
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S371000
Reexamination Certificate
active
06198152
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices allowing improved production yield and device characteristic control by employing laser trimming.
2. Description of the Background Art
In a semiconductor memory device having an MOS (Metal Oxide Silicon) configuration, spare memory cells are generally arranged in order to increase production yield. These replaced defective memory cells if necessary, in order to repair pattern defects caused in the manufacturing process.
Referring to and compared with cells shown in
FIG. 9
, a memory cell used in the present invention will be described.
With reference to
FIG. 9
, it is difficult to increase the capacity of a byte-erasable EEPROM (electrically erasable programmable ROM) because a select transistor included in the EEPROM increases the cell area. In an EPROM(erasable programmable ROM), writing is performed electrically and erase is performed collectively by ultraviolet radiation. As shown in the figure, a simple configuration having one transistor per one cell allows a small cell area. In a flash memory, collective erase performed by ultraviolet radiation in the EPROM is replaced by electrical erase achieved by charge ejection utilizing tunnel effect caused by the applied high electric field. As a result, non-volatility, electrical rewrite and erasure, and increased capacity can be obtained at the same time.
Among a number of approaches for the replacement of a spare memory cell, a laser trimming method (hereinafter is referred to as LT method) is commonly performed, in which a link is blown by laser radiation to replace a defective cell with a spare one. The LT method is also used for the fine control of reference voltage, for example, generated in the semiconductor device.
Conventionally a final protection film is formed after the LT blow process in order to prevent water and contamination from entering through the portion blown by LT process. In this approach, however, pattern defect which occurred in the final process after yield-enhancing LT blow cannot be corrected. Further, particle are generated at the time of LT blow, increasing pattern defect.
To solve the above mentioned problem, in some cases the LT blow process is performed after the formation of the final protection film. This case will be described referring to the figures.
FIG. 10
is a sectional view of a semiconductor device having an LT link portion (fuse portion).
Referring to
FIG. 10
, a P well
2
and an N well
3
are formed on the main surface of a semiconductor substrate
1
. An isolation oxide film
5
is formed in the main surface of P well
2
. An LT link
8
is formed on isolation oxide film
5
. A gate electrode
7
is also formed on P well
2
with a gate insulation film
6
posed therebetween. At each side of gate electrode
7
, are formed N type diffusion layers
10
which are to be source/drain of an N type channel transistor (NchTr).
A side wall spacer
9
is formed on the sidewall of gate electrode
7
. A P type channel transistor (PchTr) is formed in N well
3
. The P type channel transistor includes a gate insulation film
6
, a gate electrode
7
and P type diffusion layers
11
which are to be source/drain of the P type channel transistor. An interlayer insulation film
12
formed of a BPSG film and the like is provided on semiconductor substrate
1
so as to cover gate electrode
7
and LT link
8
.
A contact hole
13
is formed in interlayer insulation film
12
in order to expose the surfaces of P type diffusion layer
11
, N type diffusion layer
10
and LT link
8
. An interconnection
14
formed of aluminum alloy and so on is connected to LT link
8
, N type diffusion layer
10
and P type diffusion layer
11
through contact hole
13
. A final protection film
15
is formed on interlayer insulation film
12
so as to cover interconnection
14
. Referring to
FIG. 11
, laser trimming of LT link
8
allows the replacement of a defective memory cell with a spare memory cell.
In the conventional system, however, as can be seen from
FIG. 11
, semiconductor substrate
1
is exposed at the blown LT link. Therefore water and contamination such as sodium (Na) may easily enter the semiconductor device from outside through the exposed portion. When water or contamination enters the semiconductor device region where an active element resides, characteristics of transistors may fluctuate. Especially in the case of a non-volatile semiconductor memory device such as an EPROM and a flash memory, stored content which has been retained may volatilize, and a defect may be induced leading to the reliability degradation of the semiconductor device.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above described problems, and an object is to provide a semiconductor device having a high reliability even after the LT blow following the formation of a final protection film.
In accordance with a first aspect of the invention, a semiconductor device includes a semiconductor substrate. In the main surface of the semiconductor substrate, a field oxide film for isolating element regions from each other is formed. On the field oxide film, a link to which laser trimming is to be performed is formed. An N well is formed under the field oxide film and in the surface of the semiconductor substrate. The N well is formed of a retrograde well.
According to the present invention, substances such as sodium ions entering from an opening of the semiconductor device cannot reach an active region. As the opening formed by LT blow resides in an N well region, entering substances are gettered by N type impurity in the N well. Thus a highly reliable semiconductor device can be obtained.
In a semiconductor device according to a second aspect, when a depth into the surface of the semiconductor substrate is plotted on abscissa and impurity concentration on ordinate, the impurity concentration profile of the retrograde well has at least two concentration peaks. This impurity concentration profile achieves an efficient distribution of N type impurity in the N well.
In a semiconductor device according to a third aspect, among a plurality of concentration peaks, the impurity concentration of the peak at the deepest point in the surface of the semiconductor substrate is higher than that of another peak. In accordance with the present invention, sodium ions and so on entering from the opening formed by LT blow is efficiently gettered by high concentration N type impurity.
According to a fourth aspect of the invention, the deepest peak resides at 1-3 micrometers in the surface of the semiconductor substrate. This invention provides relatively deep N well.
A semiconductor device according to a fifth aspect provides the concentration of the N type impurity at the deepest peak of 1×10
17
atoms/cm
3
. In the present invention, a high concentration of N type impurity allows an efficient gettering of sodium ions and so on entering through the opening after the LT blow process.
In a semiconductor device according to a sixth aspect, the N type impurity is formed of P (phosphorous).
As P easily enters a crystal lattice, the use of P as an N type impurity is convenient for the formation of N well.
In a semiconductor device according to a seventh aspect, an MOSFET is formed in the element region. The MOSFET having a high reliability is provided in accordance with the present invention.
In a semiconductor device according to an eighth aspect, an EPROM is formed in the element region. The EPROM having a high reliability is provided in accordance with the present invention.
In a semiconductor device according to a ninth aspect, an EEPROM is formed in the element region. In this invention, The EEPROM attains a high reliability.
In a semiconductor device according to a tenth aspect, a flash memory is formed in the element region. A flash memory according to the present invention achieves a high reliability.
According to an eleventh aspect, a semiconductor
Carroll J.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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