Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1998-02-25
2001-03-13
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
Reexamination Certificate
active
06201297
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and to a method of producing the same. More particularly, the invention relates to technology effective in decreasing the thickness of a package of the surface mount type.
Modern engineering work stations and personal computers require a memory of a small size, yet a sufficiently large capacity to be capable of processing large amounts of data at high speeds. To meet this requirement, technology has been advanced for laminating packages of the surface mount type.
Decreasing the thickness of the individual surface-mount-type packages is essential for the lamination, and various kinds of thin packages have been developed.
For example, Japanese Patent Laid-Open No. 175406/1993 discloses thin packages, such as a TSOP (thin small outline package) and a TSOJ (Thin Small Outline J-lead package) having a semiconductor chip disposed on a chip-mounting portion (a die pad) of a lead frame, a plurality of leads arranged to surround the semiconductor chip, and a resin sealing member for sealing the inner lead portions of the plurality of leads.
There has further been proposed package having a LOC (load on chip) structure, which is one type of the surface-mount-type packages. This package has a structure in which the inner leads are partly arranged on the main surface (element-forming surface) of a semiconductor chip via an insulating tape, the ends of the inner leads are electrically connected to the bonding pads of the semiconductor chip by bonding the wires, and, then, the semiconductor chip, inner lead portions, insulating tape and bonding wires are sealed with a resin. The insulating tape is constituted by a base film of a heat-resistant resin, such as a polyimide, and an adhesive agent applied to both surfaces thereof. A package having an LOC structure of this type has been disclosed in, for example, U.S. Pat. No. 5,234,866.
SUMMARY OF THE INVENTION
The present inventors have engaged in a study to realize a surface-mount-type package having a further decreased thickness and an increased reliability, and have obtained the results as described below.
In order to prevent short-circuiting among the bonding wires caused by a flow of the wires and to prevent the appearance from becoming poor as a result of a deviated positioning of the semiconductor chip, a thin package, such as the above-mentioned TSOP and the like, have supporting leads and a chip-mounting portion (a die pad) formed integrally with the supporting leads in order to support or secure the semiconductor chip in position in the step of production, such as in the step of sealing with resin. The chip-mounting portion is arranged on the back surface of the semiconductor chip and, hence, the thickness of the surface-mount-type package increases by an amount corresponding to the thickness of the chip-mounting portion.
It is therefore difficult to provide a surface-mount-type package which maintains a high reliability, and yet has a decreased thickness.
The package of the above-mentioned LOC structure has no chip-mounting portion, unlike the above-mentioned TSOP, but has leads that are superposed on the main surface of the semiconductor chip due to its structure. Therefore, this surface-mount-type package has a thickness that is increased by an amount that corresponds to the thickness of the leads. Besides, the base film of the insulating film interposed between the semiconductor chip and the inner lead portions has a thickness of, for example, about 50 Wm, making it difficult to decrease the thickness of the package.
Moreover, the height of the loops of the bonding wires adds to the thickness of the insulating tape, resulting in an increase in the thickness of the surface-mount-type package.
When a lamination-type memory module is produced by using a packages of the LOC structure, too, it becomes difficult to decrease the thickness of the memory module for the same reasons as described above.
Moreover, the base film occupies a relatively large area in the package. Therefore, there is a likelihood that the base film will absorb moisture in the sealing resin and cause the sealing resin to be reflow-cracked.
It is further desired to decrease the cost of the semiconductor device. However, the insulating tape is generally expensive and becomes a factor contributing to an increase in the cost of the semiconductor device.
It is an object of the present invention to provide technology for decreasing the thickness of a surface-mount-type package.
Another object of the present invention is to provide technology for producing a surface-mount-type package at a decreased cost.
A further object of the present invention is to provide technology for improving the reliability and production yield of a surface-mount-type package.
A still further object of the present invention is to provide technology for decreasing the thickness of a lamination-type memory module by using surface-mount-type packages.
A yet further object of the present invention is to provide technology for decreasing the thickness of an IC card on which a surface-mount-type package is mounted.
Representative examples of the present invention are briefly described below.
A semiconductor device according to the present invention comprises:
a semiconductor chip having bonding pads formed on the main surface thereof;
a plurality of leads, each having an inner lead portion and an outer lead portion;
chip-supporting leads;
bonding wires for connecting the ends of said inner leads to said bonding pads; and
a resin sealing member for sealing said semiconductor chip, said inner lead portions, said bonding wires and said chip-supporting leads; wherein
the ends of said inner lead portions are arranged along the outer periphery of said semiconductor chip and are positioned within the thickness of said semiconductor chip in the direction of thickness of said semiconductor chip;
said outer lead portions outwardly extend from the side surfaces of said resin sealing member; and
portions of said chip-supporting leads are arranged on the main surface of said semiconductor chip and are adhered to the main surface of said semiconductor chip via an adhesive.
Furthermore, the semiconductor device of the present invention comprises:
a mounting substrate on which are formed a plurality of wirings;
a first surface-mount-type package disposed on aid mounting substrate; and
a second surface-mount-type package laminated on said first surface-mount-type package; wherein
each of said first and second surface-mount-type packages comprises:
a semiconductor chip having bonding pads formed on the main surface thereof;
a plurality of leads, each having an inner lead portion and an outer lead portion;
chip-supporting leads;
bonding wires for connecting the ends of said inner lead portions to said bonding pads; and
a resin sealing member for sealing said semiconductor chip, said inner lead portions, said bonding wires and said chip-supporting leads; wherein
the ends of said inner lead portions are arranged along the outer periphery of said semiconductor chip and are positioned within the thickness of said semiconductor chip in the direction of thickness of said semiconductor chip;
said outer lead portions outwardly extend from the side surfaces of said resin sealing member;
portions of said chip-supporting leads are arranged on the main surface of said semiconductor chip and are adhered to the main surface of said semiconductor chip via an adhesive; and
the corresponding outer lead portions of said first and second surface-mount-type packages are electrically connected together.
A method of producing a semiconductor device according to the present invention comprises the steps of:
a) preparing a semiconductor chip having bonding pads formed on the main surface thereof;
b) preparing a lead frame having an outer frame, a plurality of leads, each having an inner lead portion and an outer lead portion, and chip-supporting leads, said plurality of leads and said chip-supporting leads being formed integrally with said outer frame;
c) arran
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Potter Roy
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