Semiconductor device

Details Semiconductor device Semiconductor device

1999-07-20

2001-01-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S205000

Reexamination Certificate

active

06175516

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more specifically, the invention relates to a memory cell array system capable of accessing (inputting and outputting) an ultra-large number of bits in a dynamic memory simultaneously.
In connection with various semiconductor memory devices that have been studied by the inventor of this invention, such as DRAMs, there have been growing demands on the memory chip for an increased number of bits to increase the effective band width (frequency×number of input/output bits) of the semiconductor memory system. However, it is not easy to realize an input/output width having an ultra-large bit number, more than 32 bits, such as 128 bits, while preventing an increase in the area of the chip. To realize this requires an improvement in the memory cell array.
A technique for constructing I/O lines in a hierarchical structure is disclosed in Japanese Patent Laid-Open No. 178158/1998, Japanese Patent Laid-Open No. 288888/1997, U.S. Pat. No. 5,657,286 (that corresponds to Japanese Patent Laid-Open No. 334985/1995) and U.S. Pat. No. 5,546,349 (that corresponds to Japanese Patent Laid-Open No. 8251/1997).
SUMMARY OF THE INVENTION
Regarding semiconductor memory devices such as the DRAMs mentioned above, the configuration of the DRAM as a basis for the present invention and the problems thereof as studied by the inventor will be explained with reference to FIGS.
17
(
a
) to
20
.
FIG.
17
a
represents an example of a non-hierarchical input/output line system, which is used in 16 Mb DRAMs and 64 Mb DRAMs. The input/output lines IO are arranged on sense amplifiers in parallel with word lines and directly connected to a main amplifier. When a column selection signal line YS is on the, bit lines (BLT, BLB) and the input/output lines IOT, IOB are connected via MOS switches in the sense amplifier. To reduce the parasitic capacitance of the input/output lines IOa, 64 Mb is formed in a 16 kW×4 kBL pair configuration with the word lines set in the direction of the shorter side, as shown in FIG.
17
b
. In this system, when multiple bit memory cells are to be accessed (read/written) simultaneously, the number of input/output lines on the sense amplifiers increases (two for each set), which in turn increases the dimension of the sense amplifiers.
In the 64 Mb synchronous DRAM of FIG.
17
b
, the number of word lines that can be selected in one bank operation is limited to two by the refresh cycle (address pin) standard. If the input and output of
16
bits are performed in the sense amplifier alternate arrangement, it is necessary to arrange four IO pairs on one sense amplifier. If 32 bits are to be input and output, eight IO pairs need to be arranged on a single sense amplifier, increasing the dimension of the sense amplifiers. Because the IO lines are non-hierarchical, the junction capacitance and line capacitance of a large number of MOS switches become a parasitic capacitance of the input/output lines IO, causing degradations in the reading and writing speeds.
FIG.
18
a
represents an example of a hierarchical input/output line system. The principle of the hierarchical input/output line system is disclosed in Japanese Patent Publication No. 59712/1992, and the principle of a technique combining the hierarchical input/output line system and the hierarchical word line system is disclosed in Japanese Patent Laid-Open No. 181292/1996. The input/output lines comprise local input/output lines LIO and main input/output lines MIO. The local input/output lines LIO are arranged on the sense amplifiers and are associated with a small number of memory cell arrays. In cross areas, the local input/output lines LIO and the main input/output lines MIO are connected by switches MOS. In the case of this figure, the switches MOS between the lines LIO and MIO are analog gates of NMOS and PMOS type. By controlling these gates using sense amplifier precharge signals BLEQ, BLEQB, the switch MOS in the activated sense amplifier is turned on and the switch MOS in the deactivated sense amplifier is turned off. The main input/output lines MIO are arranged on subword drivers perpendicular to the local input/output lines LIO and straddle a number of memory cell arrays.
The hierarchical input/output line system has the following advantages. A first advantage is that it can reduce the total parasitic capacitance associated with the local input/output lines LIO and the main input/output lines MIO and thereby can speed up accesses. A second advantage is that, by dividing the local input/output lines LIO horizontally into a number of sections, it is easier to realize x16 bits and x32 bits more easily than it is by the non-hierarchical system shown in FIGS.
17
a
and
17
b
. For example, when one word line is selected in FIG.
18
a
, a number of main input/output line MIO pairs are picked up vertically along a column of subword drivers by the LIO-MIO switch in the cross area. It is, however, significantly harder to realize x64 bits or more. The reason for this is that, because the main input/output lines MIO are arranged on the subword drivers in parallel with the column selection signal lines YS, the number of bits is limited by the number of subword driver columns. If x64 bits or more are to be realized, the number of MOS switches in the cross area increases and the number of MIOs on the subword drivers also increases, making the layout more difficult.
FIGS.
19
a
and
19
b
represent circuits associated with a memory cell array, also showing subword driver areas
17
(word drivers in the hierarchical word line system) adjacent to a memory cell array area
15
and also a sense amplifier area
16
. Sense amplifier drivers and LIO-MIO switches are arranged in cross areas where the sense amplifiers and the subword drivers cross each other (in the hierarchical word line system, cross areas where shared sense amplifiers (shared by upper and lower memory cell arrays) and word drivers cross each other). It is assumed that overdrive sense amplifiers using VDDCLP are used. In this way, a large number of circuits need to be arranged in narrow cross areas defined by the sense amplifiers and the subword drivers and the layout is significantly more difficult. The hierarchical input/output line system requires incorporating LIO-MIO switches, LIO half-precharge circuits thereby and MIO distributed high-precharge circuits, making the layout very difficult. Further, increasing the number of bits to more that 64 bits increases the number of LIO-MIO switches. The number of main input/output line MIO pairs extending vertically increases as the number of bits increases and this is a limiting factor affecting the subword driver area.
FIG. 20
is an explanatory diagram showing how the parasitic capacitance is reduced in the hierarchical input/output line system. The hierarchical input/output lines aim to reduce the total parasitic capacitance of lines LIO and MIO by dividing the local input/output lines LIO and the main input/output lines MIO. The parasitic capacitance of the local input/output lines LIO is the sum of the line capacitance of a second metal line hierarchy M
2
and the junction capacitance of m YS switches MOS in the sense amplifier when the lines cross one to four memory cell arrays. The parasitic capacitance of the main input/output lines MIO is the sum of the line capacitance of a third metal line hierarchy M
3
and the junction capacitance of LIO-MIO switches MOS in the cross area when the lines cross 2n memory cell arrays. The LIO parasitic capacitance of a deactivated memory cell array is not seen. Hence, the occasions where the hierarchical input/output line system is greatly effective in capacitance reduction are when the parasitic capacitance of the local input/output lines LIO is large (LIO are shared by a large number of memory cell arrays arranged in a horizontal direction) and when the value n is large. The junction capacitance of the LIO-MIO switches MOS in the cross area increases as the MOS dimension increases. Wh

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